公开(公告)号：JP2006074031A

公开(公告)日：2006-03-16

申请号：JP2005235451

申请日：2005-08-15

Applicant: Staktek Group Lp ,  スタクテック・グループ・エルピー

Inventor： GOODWIN PAUL ,  CADY JAMES W ,  WEHRLY JAMES DOUGLAS JR

IPC: H05K1/14 ,  G11C5/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H05K1/05 ,  H05K1/11 ,  H05K1/18 ,  H05K7/20

CPC classification number: H05K1/189 ,  G11C5/04 ,  H01L25/105 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a packaging technology which reduces an increase in packaging volume accompanied by an increase in capacity. SOLUTION: Each flexible circuit is arranged with integrated circuits (ICs) disposed along one or both of its major sides, and bent around the edge of a rigid thermally-conductive substrate, thus placing ICs on one or both sides of the substrate with one or two layers of ICs on one or both sides of the substrate. On the side of the flexible circuit closest to the substrate, ICs are disposed at least partially in places which are windows, pockets, or cutaway areas in the substrate. The substrate material can be removed to reduce a module profile. An extension of the substrate reduces a thermal module load and encourages reduction in thermal variation among the ICs of the module during operation. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种包装技术，其随着容量的增加而减少包装体积的增加。

解决方案：每个柔性电路布置有沿着其主要侧面中的一个或两个侧面设置的集成电路（IC），并且围绕刚性导热基板的边缘弯曲，从而将IC放置在基板的一侧或两侧 在衬底的一侧或两侧上具有一层或两层IC。 在靠近基板的柔性电路的一侧，IC至少部分地设置在基板中的窗口，凹穴或切口区域的位置。 可以去除衬底材料以减少模块轮廓。 衬底的延伸减少了热模块的负载，并且有助于在操作期间模块的IC之间的热变化减小。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：GB2395367A

公开(公告)日：2004-05-19

申请号：GB0406140

申请日：2002-10-25

Applicant: STAKTEK GROUP LP

Inventor： CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L ,  WEHRLY JAMES DOUGLAS ,  DOWDEN JULIAN ,  BUCHLE JEFF

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48 ,  H05K1/00

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module (10) devised in accordance with a preferred embodiment of the present invention, a pair of CSPs (12, 14) is stacked, with one CSP (12) above the other (14). The two CSPs are connected with a pair of flexible circuit structures (30, 32). Each of the pair of flexible circuit structures (30, 32) is partially wrapped about a respective opposite lateral edge (20, 22) of the lower CSP (14) of the module (10). The flex circuit pair (30, 32) connects the upper and lower CSPs (12, 14) and provides a thermal and electrical path connection path between the module (10) and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.

公开(公告)号：WO2004112128A3

公开(公告)日：2005-07-14

申请号：PCT/US2004016347

申请日：2004-05-25

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  ROPER DAVID ,  BUCHLE JEFF

Inventor： CADY JAMES ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  ROPER DAVID ,  BUCHLE JEFF

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing such mounted devices for stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Abstract translation: 本发明提供一种将集成电路器件安装到衬底上的系统和方法，以及用于使用这种安装的器件用于堆叠模块的系统和方法。 封装的集成电路器件的接触焊盘基本上露出。 将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。 集成电路器件定位成与衬底的触点接触。 施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。 形成的接头在随后的加工步骤中较少受到再熔化。 该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中所公开的那些。 通常，创建的关节的轮廓较低。

公开(公告)号：WO2006121488A3

公开(公告)日：2008-01-03

申请号：PCT/US2006007192

申请日：2006-02-28

Applicant: STAKTEK GROUP LP ,  WEHRLY JAMES DOUGLAS JR ,  WOLFE MARK ,  GOODWIN PAUL

Inventor： WEHRLY JAMES DOUGLAS JR ,  WOLFE MARK ,  GOODWIN PAUL

IPC: H05K7/20 ,  H01R12/16 ,  H05K1/00 ,  H05K7/00

CPC classification number: H05K1/189 ,  H01L25/0652 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. A rigid substrate is configured to provide space on one side where the populated flex is disposed while in some embodiments, heat management or cooling structures are arranged on one side of the module to mitigate thermal accumulation in the module.

Abstract translation: 灵活的电路填充有沿其主要一侧或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 刚性基板被配置为在其上布置有人造弹性体的一侧上提供空间，而在一些实施例中，热管理或冷却结构布置在模块的一侧以减轻模块中的热积聚。

公开(公告)号：WO2007136927A2

公开(公告)日：2007-11-29

申请号：PCT/US2007065006

申请日：2007-03-27

Applicant: STAKTEK GROUP LP ,  WEHRLY JR JAMES DOUGLAS

Inventor： WEHRLY JR JAMES DOUGLAS

IPC: H01L23/02 ,  H01L21/48

CPC classification number: H01L23/5387 ,  G06K19/07732 ,  H01L23/5388 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure (106) to create an IC-populated structure. In a preferred embodiment, leads (24) of constituent leaded IC packages (20, 22) are configured to allow the lower surface (25) of the leaded IC packages (20, 22) to contact respective surfaces (15, 17) of the flex circuitry structure (106). Contacts for typical embodiments are supported by a rigid portion (120R) of the flex circuitry structure (106) and the IC-populated structure is disposed in a casing (104) to provide card structure for the module.

Abstract translation: 本发明提供一种在存储卡中采用引线封装的存储器件的系统和方法。 引线封装的IC设置在柔性电路结构（106）的一侧或两侧以产生IC填充的结构。 在优选实施例中，构成的引线IC封装（20,22）的引线（24）被配置为允许引线IC封装（20,22）的下表面（25）与相应的表面（15,17）接触 柔性电路结构（106）。 用于典型实施例的接触件由柔性电路结构（106）的刚性部分（120R）支撑，并且IC填充结构设置在壳体（104）中以为模块提供卡结构。

公开(公告)号：WO2007053523A3

公开(公告)日：2007-10-04

申请号：PCT/US2006042232

申请日：2006-10-27

Applicant: STAKTEK GROUP LP ,  PARTRIDGE JULIAN ,  WEHRLY JAMES DOUGLAS ,  ROPER DAVID L ,  VILLANI JOSEPH

Inventor： PARTRIDGE JULIAN ,  WEHRLY JAMES DOUGLAS ,  ROPER DAVID L ,  VILLANI JOSEPH

IPC: H01L23/52 ,  H01L25/065

CPC classification number: H01L23/49833 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H05K3/305 ,  H05K2201/056 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to add ional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.

Abstract translation: 本发明将集成电路封装堆叠到电路模块中。 在优选实施例中，分别将焊膏和主粘合剂施加到柔性电路上的选定位置。 补充粘合剂用于在柔性电路，CSP或其他组件上添加离子位置。 柔性电路和CSP彼此靠近。 在回流焊操作期间，施加力并且CSP朝柔性电路折叠，取代主粘合剂和辅助粘合剂。 补充粘合剂建立了为柔性电路提供额外支撑的粘合。 在另一个实施例中，CSP或其他集成电路封装通过粘合剂的组合彼此粘合或粘合到其他组件。 快速粘合粘合剂在组装期间保持粘合的封装和/或部件的对齐，并且结构粘合粘合剂为粘合提供额外的强度和/或结构完整性。

公开(公告)号：WO2005098941A3

公开(公告)日：2006-07-13

申请号：PCT/US2005010756

申请日：2005-03-30

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  WILDER JAMES ,  ROPER DAVID ,  WEHRLY JR DOUGLAS

Inventor： CADY JAMES ,  WILDER JAMES ,  ROPER DAVID ,  WEHRLY JR DOUGLAS

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/31 ,  H01L23/34 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules 10 provided herewith. In a preferred embodiment in accordance with the invention, a form standard 34 provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design 32. In a preferred embodiment, the form standard 34 will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard 34 may include a heat spreader portion 192 with mounting feet 198. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module 10 to reduce the loading effect upon data signals in memory access.

Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块10。 在根据本发明的优选实施例中，形式标准34提供允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计32时被有利地使用的物理形式。 优选实施例中，将设计出诸如铜之类的热转移材料的形式标准34以改善热性能。 在替代实施例中，形式标准34可以包括具有安装脚198的散热器部分19.在存储器寻址系统的优选实施例中，高速切换系统选择与堆叠模块10的每个级别相关联的数据线 减少存储器访问中数据信号的负载效应。

公开(公告)号：WO2005114726A2

公开(公告)日：2005-12-01

申请号：PCT/US2005016764

申请日：2005-05-11

Applicant: STAKTEK GROUP LP ,  WEHRLY DOUGLAS JR ,  CADY JAMES ,  PARTRIDGE JULIAN ,  ROPER DAVID

Inventor： WEHRLY DOUGLAS JR ,  CADY JAMES ,  PARTRIDGE JULIAN ,  ROPER DAVID

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/02

CPC classification number: H01L25/105 ,  H01L23/3114 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/107

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or more conductive layers with preferred embodiments having two conductive layers. A form standard is disposed along the lower planar surface and extends laterally beyond the package of one or more CSPs in a stacked module. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be comprised of heat conductive material such as copper, for example.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 该柔性电路可以呈现一个或多个导电层，优选实施例具有两个导电层。 形式标准沿着下平面表面设置并横向延伸超过堆叠模块中的一个或多个CSP的包装。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在优选实施例中，形式标准例如由导热材料例如铜构成。

公开(公告)号：WO2005010990A3

公开(公告)日：2005-05-06

申请号：PCT/US2004023152

申请日：2004-07-20

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  RAPPORT RUSSELL ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  WILDER JAMES ,  ROPER DAVID ,  BUCHLE JEFF

Inventor： CADY JAMES ,  RAPPORT RUSSELL ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  WILDER JAMES ,  ROPER DAVID ,  BUCHLE JEFF

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/373 ,  H01L23/485

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM. Although the present invention is preferably employed to advantage using stacked modules comprised from multiple CSPs, it may be employed with modules comprised from any number and type of integrated circuits including any type of packaging, whether CSP or leaded. The stacked modules make use of flexible substrates, low-profile contacts and form standarads for folding substrates.

Abstract translation: 通过使用堆叠模块，提供了用于多个集成存储器电路的点对点寻址的系统和方法。 单个存储器扩展板上装有集成电路的堆叠模块。 在优选实施例中，不使用堆叠的四个DIMM插槽存储器存取总线被单个DIMM插槽总线替代，该DIMM插槽总线在单个DIMM上支持堆叠高达四个高。 虽然本发明优选地使用由多个CSP组成的堆叠模块，但是可以使用包括任何数量和类型的集成电路的模块，包括任何类型的封装，无论是CSP还是带引线。 堆叠的模块使用柔性基板，低轮廓接触和形成用于折叠基板的标准。

公开(公告)号：WO2008060816A3

公开(公告)日：2008-07-24

申请号：PCT/US2007081931

申请日：2007-10-19

Applicant: STAKTEK GROUP LP ,  SZEWERENKO LELAND ,  GOODWIN PAUL ,  WEHRLY JAMES DOUGLAS JR

Inventor： SZEWERENKO LELAND ,  GOODWIN PAUL ,  WEHRLY JAMES DOUGLAS JR

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: The present invention provides a system and method for devising stackable assemblies (70) that may be then stacked to create a stacked circuit module (50). One or more integrated circuit (IC) die (12) are disposed on one or more sides of a redistribution substrate (20) that is preferably flexible circuitry. In some preferred embodiments, the die (12) and redistribution substrate (20) are bonded together and wire-bond (33) connected. Two or more stackable assemblies (70) are interconnected through frame members (30) to create low profile high density stacked circuit modules (50).

Abstract translation: 本发明提供了用于设计可堆叠组件（70）的系统和方法，所述可堆叠组件（70）然后可被堆叠以形成堆叠电路模块（50）。 一个或多个集成电路（IC）管芯（12）设置在优选为柔性电路的再分配衬底（20）的一个或多个侧面上。 在一些优选实施例中，管芯（12）和再分配基板（20）被结合在一起并且引线结合（33）被连接。 两个或更多个可堆叠组件（70）通过框架构件（30）互连以形成低轮廓高密度堆叠电路模块（50）。