公开(公告)号：EP1746604A1

公开(公告)日：2007-01-24

申请号：EP05106783.3

申请日：2005-07-22

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Bovino, Angelo ,  Altieri, Vincenzo ,  Ravasio, Roberto ,  Micheloni, Rino ,  De Matteis, Mario

IPC: G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C2211/5641

Abstract: Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.

Abstract translation: 多级编程（30-42）允许通过从第二位（MSB）单独编程（30-32）第一位（LSB）来在所选单元（3）中写入第一位和第二位。 第一位的编程（30-32）确定从第一阈值电平（A）到第二阈值电平（B）的移位（32）; 第二位的编程（36-42）需要初步读取（36-40）来检测第一位（LSB）是否已被修改; 执行第一写入步骤（42），如果第一位已被修改并使单元进入第三阈值电压（C），并执行第二写入步骤（42）以使所选择的单元达到不同的第四阈值电压（D） 如果第一位未被修改，则从第三阈值水平。 存储器阵列（2）被划分为第一部分（2a），其中使用与多个位相对应的多个阈值级别存储数据;以及第二部分（2b），其中使用与单个位对应的两个阈值电平存储数据。 为了增加读取和编程可靠性，在第二部分（2b）的初步读取（40）期间，读取结果被迫对应于第一阈值水平。

公开(公告)号：EP1635261B1

公开(公告)日：2008-06-11

申请号：EP04425678.2

申请日：2004-09-10

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Bovino, Angelo ,  Altieri, Vincenzo

IPC: G06F11/10

CPC classification number: G06F11/1048

公开(公告)号：EP1746604B1

公开(公告)日：2009-02-04

申请号：EP05106783.3

申请日：2005-07-22

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Bovino, Angelo ,  Altieri, Vincenzo ,  Ravasio, Roberto ,  Micheloni, Rino ,  De Matteis, Mario

IPC: G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C2211/5641

公开(公告)号：EP1635261A1

公开(公告)日：2006-03-15

申请号：EP04425678.2

申请日：2004-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Bovino, Angelo ,  Altieri, Vincenzo

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: A memory (104) has one bus (112) for data, addresses, and commands. A data register (114) is coupled to the bus (112) to store the data written to and read from the memory (104), a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code (ECC) circuit for calculating an ECC. The memory (104) is configured (168, 200, 206, 237) to be responsive to external commands for controlling the operation of the ECC circuit (140) for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

Abstract translation: 存储器（104）具有用于数据，地址和命令的一个总线（112）。 数据寄存器（114）耦合到总线（112）以存储写入存储器（104）和从存储器（104）读取的数据，命令寄存器耦合到总线以接收存储器命令，并且地址寄存器耦合到 总线来解决内存。 存储器还包括用于计算ECC的纠错码（ECC）电路。 存储器（104）被配置为响应于用于控制ECC电路（140）的操作的外部命令，用于读取或写入与控制读取或写入的外部命令分离的ECC 的内存数据。 存储器还可以包括状态寄存器，其存储关于ECC的通过或失败的信息。