公开(公告)号：EP1460542A1

公开(公告)日：2004-09-22

申请号：EP03425171.0

申请日：2003-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1048

Abstract: The present invention relates to an integrated memory system (1) comprising at least a non volatile memory (2) and an automatic storage error corrector, and wherein the memory (2) is connected to a controller (3) by means of an interface bus (4). Advantageously, the system comprises in the memory (2) circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal (IRQ) to ask a correction being external to the memory (2).

Abstract translation: 本发明涉及到集成存储系统（1），包括至少一个非易失性存储器（2）和自动存储误差校正器，和worin存储器（2）通过接口总线连接到控制器（3） （4）。 有利地，该系统包括：在存储器（2）的电路装置，在功能上独立的，每个负责一个预定的存储误差的修正; 产生一个信号（IRQ）问的校正是外部存储器。所述装置的至少一个（2）。

公开(公告)号：EP1912121B1

公开(公告)日：2009-08-12

申请号：EP06425632.4

申请日：2006-09-13

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

IPC: G06F11/10 ,  G06F11/20

CPC classification number: G11C29/82 ,  G06F11/1068 ,  G11C29/24 ,  G11C2029/0411

公开(公告)号：EP1752989A1

公开(公告)日：2007-02-14

申请号：EP05106976.3

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Bovino, Angelo ,  Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/32 ,  G11C16/344

Abstract: A non-volatile memory device (100) is proposed. The non-volatile memory device includes a plurality of memory cells (110) each one having a programmable threshold voltage, and means for reading (130, 140, 150) a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging (Pc) a reading node (BL) associated with the selected memory cell with a charging voltage (Vc), means for biasing (130) the selected memory cell with a biasing voltage, means for connecting (120d, 120s) the charged reading node with the biased selected memory cell, and means for sensing (205) a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages (V R ) the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay (Te), wherein for at least a second one of the reference voltages (Vga) the biasing voltage is a second biasing voltage (V R ) different from the second reference voltage, and the delay is a second delay (Teg) different from the first delay.

Abstract translation: 一种非易失性存储器设备（100）提议。 非易失性存储器设备包括存储器单元的多个（110）每一个具有可编程阈值电压的装置，以及用于读出（130，140，150）相对于一组选定的存储器单元内的基准电压复数，用于 每个所选择的存储单元中的装置，用于读取包括用于充电（PC）读出节点（BL）用的充电电压所选择的存储器单元相关联（VC），用于偏置（130）所述选定存储器单元与偏置电压， 装置，用于连接（120D，120秒）与该偏置的选定存储器单元中的电荷的读出节点的装置，以及用于感测（205）在从所述连接的预定义的延迟之后读出节点的电压，对于参考电压中的至少一个第一个 （VR）的偏置电压是一个第一偏置电压等于所述第一基准电压和所述延迟是共同的第一延迟（TE），worin对于参考电压中的至少一个第二个（VGA）的偏置电压是一个第二偏置 电压 （V R）从所述第二参考电压不同，并且延迟为第二延迟（TEG）与所述第一延迟不同。

公开(公告)号：EP1635261A1

公开(公告)日：2006-03-15

申请号：EP04425678.2

申请日：2004-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Bovino, Angelo ,  Altieri, Vincenzo

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: A memory (104) has one bus (112) for data, addresses, and commands. A data register (114) is coupled to the bus (112) to store the data written to and read from the memory (104), a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code (ECC) circuit for calculating an ECC. The memory (104) is configured (168, 200, 206, 237) to be responsive to external commands for controlling the operation of the ECC circuit (140) for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

Abstract translation: 存储器（104）具有用于数据，地址和命令的一个总线（112）。 数据寄存器（114）耦合到总线（112）以存储写入存储器（104）和从存储器（104）读取的数据，命令寄存器耦合到总线以接收存储器命令，并且地址寄存器耦合到 总线来解决内存。 存储器还包括用于计算ECC的纠错码（ECC）电路。 存储器（104）被配置为响应于用于控制ECC电路（140）的操作的外部命令，用于读取或写入与控制读取或写入的外部命令分离的ECC 的内存数据。 存储器还可以包括状态寄存器，其存储关于ECC的通过或失败的信息。

公开(公告)号：EP1435625A1

公开(公告)日：2004-07-07

申请号：EP02425808.9

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Khouri, Osama ,  Ravasio, Roberto ,  Micheloni, Rino ,  Campardo, Giovanni

IPC: G11C29/00

CPC classification number: G11C29/76

Abstract: A non volatile memory of the type comprising a predetermined number of sectors capable of ensuring the operation of the same even with a lower number of defective sectors than a predetermined limit.

Abstract translation: 这种类型的非易失性存储器包括能够确保即使具有比预定极限更少数量的缺陷扇区的扇区的预定数量的扇区。

公开(公告)号：EP1748445B1

公开(公告)日：2008-12-10

申请号：EP05106972.2

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Missiroli, Chiara ,  Bovino, Angelo ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G11C11/56

CPC classification number: G11C11/5628

公开(公告)号：EP1752989B1

公开(公告)日：2008-04-23

申请号：EP05106976.3

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Bovino, Angelo ,  Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/32 ,  G11C16/344

公开(公告)号：EP1748445A1

公开(公告)日：2007-01-31

申请号：EP05106972.2

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Missiroli, Chiara ,  Bovino, Angelo ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G11C11/56

CPC classification number: G11C11/5628

Abstract: A page buffer (130) for an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in a plurality of bit lines (BLe,BLo) of memory cells and forming a plurality of individually-selectable memory sets. The electrically programmable memory includes a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (MSB) and a second data bits group (LSB), the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets forming at least a first memory page and a second memory page, respectively. The first and second memory pages are individually addressable in reading and writing. The page buffer comprises at least one read/program unit (205) having a coupling line (SO) operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cells sets. The read/program unit comprises enabling means (230-1, 230-2, 252, 254, 256, 258, 272, 274, 276, 278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits (MSB) of the selected memory cell, and an existing data value already stored in the second group of data bits (LSB) of the selected memory cell. The enabling means comprise reading means (256, 258, 260, 230-2) for retrieving the existing data value; means (252, 254, 230-1) for receiving an indication of the target data value; combining means (272, 274, 276, 278) for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication; and conditioning means (272, 274) included in the combining means for conditioning a potential of the coupling line based on the existing data value and the modified indication, so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

Abstract translation: 提供了一种用于电可编程存储器（100）的页缓冲器（130）。 电可编程存储器包括布置在存储器单元的多个位线（BLe，BLo）中的多个存储单元（110），并形成多个单独选择的存储器组。 电可编程存储器包括针对每个存储器单元定义的多个不同的编程状态，对应于每个存储单元中可存储的数据位数N> = 2。 数据位包括至少第一数据位组（MSB）和第二数据位组（LSB），第一数据位组和分别存储在所述可单独选择的一个存储单元中的第二数据位组 存储单元组分别形成至少第一存储器页面和第二存储器页面。 第一和第二个存储器页面在读取和写入时可单独寻址。 页面缓冲器包括至少一个具有可操作地与至少一个所述位线相关联的耦合线（SO）的读/写单元（205），并且适于至少临时存储从或写入 存储在所选存储单元组的存储单元中的第一或第二存储器页。 读/程序单元包括启用装置（230-1,230-2,252,254,256,258,272,274,276,278,278,276,278,272,276,278,276,278,278,276,278,276,278,278,276,278,278,276,278,278,276,278,278,276,278,278,278,276,278,278,278,276,278,278,2 行程序中的一个，使程序启用电位和程序禁止电位，调节为要存储在所选择的存储器单元的第一组数据位（MSB）中的目标数据值，以及已经存储在第二个存储单元中的现有数据值 所选存储单元的数据位组（LSB）组。 启用装置包括用于检索现有数据值的读取装置（256,258,260,230-2）; 用于接收目标数据值的指示的装置（252,254,230-1）; 用于将接收到的目标数据值与所检索的现有数据值组合的组合装置（272,274,276,278），从而修改目标数据值的所述指示以获得修改的指示; 以及包括在组合装置中的调节装置（272,274），用于基于现有数据值和修改的指示调节耦合线的电位，以使耦合线采取程序使能电位或编程抑制电位 。

公开(公告)号：EP1746604A1

公开(公告)日：2007-01-24

申请号：EP05106783.3

申请日：2005-07-22

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Bovino, Angelo ,  Altieri, Vincenzo ,  Ravasio, Roberto ,  Micheloni, Rino ,  De Matteis, Mario

IPC: G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C2211/5641

Abstract: Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.

Abstract translation: 多级编程（30-42）允许通过从第二位（MSB）单独编程（30-32）第一位（LSB）来在所选单元（3）中写入第一位和第二位。 第一位的编程（30-32）确定从第一阈值电平（A）到第二阈值电平（B）的移位（32）; 第二位的编程（36-42）需要初步读取（36-40）来检测第一位（LSB）是否已被修改; 执行第一写入步骤（42），如果第一位已被修改并使单元进入第三阈值电压（C），并执行第二写入步骤（42）以使所选择的单元达到不同的第四阈值电压（D） 如果第一位未被修改，则从第三阈值水平。 存储器阵列（2）被划分为第一部分（2a），其中使用与多个位相对应的多个阈值级别存储数据;以及第二部分（2b），其中使用与单个位对应的两个阈值电平存储数据。 为了增加读取和编程可靠性，在第二部分（2b）的初步读取（40）期间，读取结果被迫对应于第一阈值水平。

公开(公告)号：EP1729306A1

公开(公告)日：2006-12-06

申请号：EP05104742.1

申请日：2005-06-01

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Motta, Ilaria

IPC: G11C16/34

CPC classification number: G11C16/3404 ,  G11C16/3409

Abstract: A flash memory device with NAND architecture (100) is proposed. The memory device includes a matrix of memory cells (110) each one having a programmable threshold voltage, wherein the matrix includes at least one sector individually erasable (115) and it is arranged in a plurality of rows and columns with the cells of each row connected to the corresponding word line (WL) and the cells of each column arranged in a plurality of strings (125) of cells connected in series, the strings of each column being connected to a corresponding bit line (BL), wherein the memory device further includes means (320) for erasing the cells of a selected sector, and means (330) for restoring the threshold voltage of the erased cells, wherein the means for restoring acts in succession on each of a plurality of blocks of the sector, for each one of a set of selected bit lines the block including a group of cells connected to a set of selected word lines, the means for restoring including means (446a, 446b) for reading each group with respect to a limit value exceeding a reading reference value, means (451a, 451b) for programming only each group wherein the threshold voltage of at least one group does not reach said limit value, and means (449a, 449b) for stopping the restoring in response to the reaching of the limit value by at least one sub-set of the groups.

Abstract translation: 提出了具有NAND架构（100）的闪存器件。 存储器件包括每个具有可编程阈值电压的存储器单元（110）的矩阵，其中该矩阵包括至少一个可单独地擦除的扇区（115），并且它被布置成多个行和列，每行的单元格 连接到相应的字线（WL）和排列成串联连接的多个单元串（125）的每列的单元，每列的串连接到对应的位线（BL），其中存储器件 还包括用于擦除所选扇区的单元的装置（320），以及用于恢复已擦除单元的阈值电压的装置（330），其中用于恢复的装置依次在该扇区的多个块中的每个块上作用， 一组选定位线中的每一个，包括连接到一组所选字线的一组单元的单元，所述恢复装置包括用于相对于超过一个限制值的每个组读取每个组的装置（446a，446b） 读取参考值，用于仅编程至少一个组的阈值电压未达到所述极限值的每个组的装置（451a，451b）以及用于响应于达到极限而停止恢复的装置（449a，449b） 至少一个组的子集的值。