公开(公告)号：EP1132959A1

公开(公告)日：2001-09-12

申请号：EP00830162.4

申请日：2000-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Atti, Massimo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/8246

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal (CG), a second terminal (D), and a third terminal (S) connected, respectively, to a row line (WLi), to a column line (BLi), and to a common node by respective connection strips (CG, R). In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer (I2) which covers the connection strips of the first terminals (CG) and of the third terminals (S), the formation of channels (CH1, CH2) along the connection strips until the surfaces thereof are exposed, and the filling of the channels (CH1, CH2) with a material (W) having a resistivity lower than that of the connection strips.

Abstract translation: 该方法适用于具有排列成行和列的单元的非易失性半导体存储器，其中每个单元具有分别连接到第一端子（CG），第二端子（D）和第三端子（S）的单元 行线（WLi）到列线（BLi），并且通过相应的连接条（CG，R）连接到公共节点。 为了形成具有低电阻率的连接并因此节省半导体面积，该方法提供了覆盖第一端子（CG）和第三端子（S）的连接条的氧化物层（I2）的形成， 沿着连接条形成通道（CH1，CH2），直到其表面露出，并且用具有低于连接条的电阻率的材料（W）填充通道（CH1，CH2）。

公开(公告)号：EP1191601B1

公开(公告)日：2007-11-28

申请号：EP00830628.4

申请日：2000-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Zatelli, Nicola ,  Atti, Massimo ,  Palumbo, Elisabetta ,  Torelli, Cosimo

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L29/7835

公开(公告)号：EP1191601A1

公开(公告)日：2002-03-27

申请号：EP00830628.4

申请日：2000-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Zatelli, Nicola ,  Atti, Massimo ,  Palumbo, Elisabetta ,  Torelli, Cosimo

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L29/7835

Abstract: A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract translation: 一种具有漏极区域（13,14）的横向DMOS晶体管，包括漏电极（D）与其接触的高浓度部分（14）和由沟道区域限定的低浓度部分（13） 。 除了传统的源极，漏极，主体和栅极之外，晶体管具有与漏极区域（13,14）的靠近沟道的低浓度部分的点接触的附加电极（25）。 附加电极允许直接测量栅极电介质中的电场，并且因此提供可用于表征晶体管并选择其尺寸的信息，并且用于激活用于保护晶体管和/或其中包含的集成电路的其它部件的器件 晶体管。