公开(公告)号：EP3648349A1

公开(公告)日：2020-05-06

申请号：EP19203837.0

申请日：2019-10-17

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ALAGNA, Diego ,  ERRICO, Nicola ,  CIGNOLI, Marco ,  DE AGOSTINI, Gian Battista

IPC: H03K7/08 ,  H02M3/157

Abstract: A PWM signal generator (12) configured (D) to provide a supply current (I LOAD ) to an electrical load (L) generates PWM signals at a first frequency (f PWM ), the PWM signals having a duty cycle.
Operating the generator involves:
- receiving a set point signal (SP) indicative of a target average value for the supply current (I LOAD ),
- sensing (20) a sensing signal indicative of a current actual value of the supply current (I LOAD ),
- performing a closed-loop control of the supply current (I LOAD ) targeting the target value (SP) for the supply current via a controller (14; 141, 142, 143, 144) such as a PID Controller which controls (PID) the duty cycle of the PWM signals generated by the PWM signal generator (12) as a function of the offset (18) of the sensing signal with respect to the set point signal (SP).

公开(公告)号：EP4290254A1

公开(公告)日：2023-12-13

申请号：EP23174170.3

申请日：2023-05-18

Applicant: STMicroelectronics S.r.l.

Inventor： ALAGNA, Diego ,  CANNONE, Alessandro

IPC: G01R31/317

Abstract: Circuit arrangement for validation of operation of a logic module (11) in a multipower logic architecture (10), comprising
at least a first logic module (11) operating with a first clock signal (MCK) and a first power supply (VMP), and
a second logic module (12) operating with a second clock signal (SCK) and second power supply (VMP),
said first logic module (11) and second logic module (12) being configured to exchange signals at least on a communication link (DL), wherein
the first logic module (11) is configured to generate a first validation signal (A) and a second validation signal (B), in particular on a first and second wire respectively, which are sent over the communication link (DL) to the second logic module (12), the values of said first validation signal (A) and second validation signal (B) being never zero at the same time,
the second logic module (12) being configured to
perform a first check that the second validation signal (B) is always logic one when the first validation signal (A) is zero,
perform a second check that the first validation signal (A) is always logic one when the second validation signal (B) is zero,
perform a cyclic check that the first validation signal (A) and the second validation signal (B) are not stuck-at-1, and
to validate (MV) the operation of the first logic module (A) if said first check, second check and cyclic check give each a positive result.

公开(公告)号：EP4113840A1

公开(公告)日：2023-01-04

申请号：EP22180456.0

申请日：2022-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： D'ANGELO, Vittorio ,  CANNAVACCIUOLO, Salvatore ,  BENDOTTI, Valerio ,  SELVO, Paolo ,  ALAGNA, Diego

IPC: H03K17/18 ,  H03K17/689

Abstract: An isolated gate driver device (10) has: a low-voltage section (10a), having a control input (IN PWM ), which receives a PWM control signal (S PWM ) at a switching frequency (f PWM_HV ); a high-voltage section (10b), galvanically isolated from the low-voltage section, having a driving output (OUT DRV ), which provides a gate-driving signal (V G ), as a function of the PWM control signal, to a switch (18) of a power stage (14), and a feedback input (IN FB ), which receives at least one feedback signal (S FB ) indicative of the operation of the power stage; and a communication channel (15), which implements an isolated communication between the low-voltage and high-voltage sections. The high-voltage section comprises an ADC module (22), which converts the feedback signal into a digital data stream, and a conversion-control module (24), coupled to the ADC module for providing a conversion-trigger signal (S Trig ) that determines the start of conversion for acquisition of a new sample (S k ) of the feedback signal.

公开(公告)号：EP4270206A1

公开(公告)日：2023-11-01

申请号：EP23162258.0

申请日：2023-03-16

Applicant: STMicroelectronics S.r.l.

Inventor： OREGGIA, Daniele ,  CANNONE, Alessandro ,  ALAGNA, Diego ,  RAIMONDI, Marcello

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L12/40 ,  H01M10/42

Abstract: A battery management system includes: a controller (211); a master battery management integrated circuit, BMIC, device (213M) coupled to the controller (211) and configured to communicate with the controller (211) through a standard Serial Peripheral Interface, SPI, protocol; and a first slave BMIC device (213SA) and a second slave BMIC device (213SB) that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device (213 SA) is coupled to the master BMIC device (213M) through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device (213SA) and the second slave BMIC device (213SB) are configured to be coupled to a first battery pack and a second battery pack, respectively.

公开(公告)号：EP3926348A1

公开(公告)日：2021-12-22

申请号：EP21178626.4

申请日：2021-06-09

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ERRICO, Nicola ,  VILMERCATI, Paolo ,  CIGNOLI, Marco ,  GENNA, Vincenzo Salvatore ,  ALAGNA, Diego

IPC: G01R19/00 ,  G01R19/165 ,  H02M1/00

Abstract: A circuit (100') comprises a high-side switch (HS) and a low-side switch (LS) arranged between a supply node (D) and a reference node (G), the high-side and low-side switches having an intermediate node (Q). A switching control signal ( com ) is applied with opposite polarities to the high-side and low-side switches. An inductive load (L) is coupled between the intermediate node (Q) and one of said supply node (D) and said reference node (G).
The circuit (100') further comprises current sensing circuitry (CS') configured to:
sample (12a, 14a) a first value ( I a ) of the load current flowing in one of the high-side and low-side switches at a first sampling instant ( t 1 ) before a commutation ( t s ) of the switching control signal ( com ),
sample (12b, 14b) a second value ( I b ) of the load current flowing in the other of the high-side and low-side switches at a second sampling instant ( t 2 ) after said commutation ( t s ) of said switching control signal ( com ),
sample (12b, 14c) a third value ( I c ) of the load current flowing in the other of the high-side and low-side switches at a third sampling instant ( t 3 ) after said second sampling instant ( t 2 ), and
generate (18) a failure signal ( fail ) as a function of said first ( I a ), second ( I b ) and third ( I c ) sampled values of the load current.