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    Temperature correlated voltage generator circuit and corresponding voltage regulator for a single power memory cell, particularly of the FLASH-type
    6.
    发明公开
    Temperature correlated voltage generator circuit and corresponding voltage regulator for a single power memory cell, particularly of the FLASH-type 失效
    温度相关电压发生器电路和用于提供与单个电源上的存储器单元相关联的电压调节器，特别是闪存类型的

    公开(公告)号：EP0915407A1

    公开(公告)日：1999-05-12

    申请号：EP97830574.6

    申请日：1997-11-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mulatti, Jacopo ,  Zammattio, Matteo ,  Ghilardelli, Andrea ,  Carrera, Marcello

    IPC: G05F1/00 ,  G05F3/24

    CPC classification number: G05F3/245 ,  Y10S323/907

    Abstract: The invention relates to a temperature-related voltage generating circuit having an input terminal (15) receiving a control voltage (V BG ) independent of temperature, and an output terminal (16) delivering a temperature-related control voltage (Vout), the input and output terminals (15, 16) being connected together through at least an amplifier stage (19) adapted to set an output reference voltage from a comparison of input voltages, and comprising a generator element (T1) generating a Varying voltage (V BE ) with temperature connected between a ground voltage reference (GND) and a non-inverting input terminal of the amplifier stage (19), which has an output terminal adapted to deliver a multiple of the varying voltage (V BE ) with temperature to an inverting input terminal of a comparator stage (18); the comparator stage (18) has its output connected to the temperature-related voltage generating circuit (14) and a non-inverting input terminal receiving the control voltage (V BG ) independent of temperature to evaluate the difference between the control voltage (V BG ) independent of temperature and said voltage being a multiple of the varying voltage (V BE ) with temperature and to output a temperature-related control voltage (Vout) having at room temperature a mean value which is independent of its thermal differential (δVout/δT) and increases with temperature.
    The invention also relates to a regulator for a drain voltage (Vd) of a single-supply memory cell (M1), comprising a temperature-related voltage generating circuit (14) according to the invention.

    Abstract translation: 本发明涉及具有输入端子（15）的温度相关的电压生成电路接收控制电压（VBG）与温度无关，并提供一个温度相关的控制电压（Vout），所述输入输出端子（16）和 输出端子（15，16）通过连接在一起的至少到放大器级（19）angepasst从输入电压的比较，并包括发电机元件（T1）产生变化的电压（VBE）与温度设定为输出参考电压 连接在地电压基准（GND）和所述放大器级（19），其具有与输出端子angepasst以反转的输入端子提供变化的电压（VBE）随温度的倍数的一个非反相输入端之间 比较器级（18）; 的比较器级（18）具有其输出连接到所述温度有关的电压发生电路（14）和一个非反相输入端接收与温度无关的控制电压（VBG），以评估（VBG）独立于控制电压之间的差 温度和所述电压是所述变化的电压（VBE）的随温度和输出的平均值的所有其是独立于其热差异的（增量比Vout /增量T）在室温下具有的温度相关的控制电压（Vout）的倍数的 随着温度增加而增加。 因此，本发明涉及一种用于一个温度相关的电压发生电路（14）的单电源的存储单元（M1）的漏极电压（Vd）的调节器雅丁于本发明。

    Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages
    8.
    发明公开
    Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages 有权
    行解码器，用于非易失性存储器为字线随机正和负偏置调整

    公开(公告)号：EP1061525A1

    公开(公告)日：2000-12-20

    申请号：EP99830378.8

    申请日：1999-06-17

    Applicant: STMicroelectronics S.r.l. ,  Mitsubishi Electric Corporation

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ohba, Atsushi, c/o Mitsubishi Denki K. K. ,  Carrera, Marcello

    IPC: G11C16/12 ,  G11C8/00

    CPC classification number: G11C11/5621 ,  G11C8/08 ,  G11C8/14 ,  G11C16/08 ,  G11C16/12 ,  G11C16/30

    Abstract: The row decoder includes, for each word line (WL) of the memory (2), a respective biasing circuit (54) receiving at the input a row selection signal (SR ) switching, in preset operating conditions, between a supply voltage (V CC ) and a ground voltage (V GND ) and supplying at the output a biasing signal (R ) for the respective word line (WL) switching between a first operating voltage (V PC ), in turn switching at least between the supply voltage (V CC ) and a programming voltage (V PP ) higher than the supply voltage (V CC ), and a second operating voltage (V NEG ), in turn switching at least between the ground voltage (V GND ) and an erase voltage (V ERN ) lower than the ground voltage (V GND ). Each biasing circuit (54) includes a level translator circuit (58) receiving at the input the row selection signal (SR ) and supplying as output a control signal (CM ) switching between the first and the second operating voltages (V PC , V NEG ) and an output driver circuit (60) receiving as input the control signal (CM ) and supplying at the output the biasing signal (R ).

    Abstract translation: 行译码器包括，用于存储器（2），一个respectivement偏置电路（54）的每个字线（WL）在所述输入端接收一个行选择信号（SR的）的切换，在预先设定的操作条件下，一个电源之间 电压（VCC）和地电压（V GND），并在输出端供给的respectivement字线的第一工作电压（VPC）之间进行切换的偏置信号（R ）（WL），依次之间至少切换 电源电压（VCC）和一个编程电压（VPP）高于电源电压（VCC），和第二操作电压（VNEG），继而至少接地电压（V GND）和擦除电压（VERN）低之间切换更高 比接地电压（V GND）。 每个偏置电路（54）包括：在输入端接收所述行选择信号（SR的）和供应作为输出的控制信号的电平转换电路（58）（CM的）在第一和第二工作电压之间的切换 （VPC，VNEG）和接收作为输入的控制信号输出驱动器电路（60）（CM的），并在输出端供给所述偏压信号（R ）。

    CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching
    9.
    发明公开
    CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching 有权
    CMOS开关期间在非易失性存储器的低功耗切换用于传输高电压，特别是对行译码器

    公开(公告)号：EP1058271A1

    公开(公告)日：2000-12-06

    申请号：EP99830345.7

    申请日：1999-06-04

    Applicant: STMicroelectronics S.r.l. ,  Mitsubishi Electric Corporation

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ohba, Atsushi, c/o Mitsubishi Denki K. K. ,  Carrera, Marcello

    IPC: G11C16/12 ,  H03K19/017

    CPC classification number: H03K19/018521 ,  G11C5/145 ,  G11C8/10 ,  G11C11/5621 ,  G11C16/08 ,  H03K19/0013 ,  H03K19/01721

    Abstract: The switch circuit (40) receives a first supply voltage (V CC ) and a second supply voltage (V PP ) different from each other; a control input (41a) receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage (44) supplied by the second supply voltage (V PP ) and defining the output (70) of the circuit; a feedback inverter stage (43) supplied by the second supply voltage and including a top transistor (51) and a bottom transistor (53) defining an intermediate node (58) and having respective control terminals. The control terminal of the top transistor (51) is connected to the output node (70), the control terminal of the bottom transistor (53) is connected to the control input (41a), and the intermediate node is connected to the input (58) of the driving inverter stage. An activation element (80, 71) helps switching of the intermediate node (58) from the second supply voltage to ground; current limiting transistors (52, 62) are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.

    Abstract translation: 开关电路（40）接收第一供给电压（VCC）和第二电源电压（VPP）从海誓山盟不同; 接收控制信号的控制输入端（41）可以被切换所述第一电源电压和地之间做; 由第二电源电压（VPP）和，定义电路的输出（70）提供的驱动逆变器级（44）; 由第二电源电压供电，并且包括一个顶部晶体管（51）和上限定中间节点（58）和具有respectivement控制端子的底部晶体管（53）的反馈逆变器级（43）。 顶部晶体管的控制端子（51）被连接到被连接到控制输入端（41A）和中间节点的输出节点（70），底部晶体管的控制端子（53）被连接到输入端（ 驱动用逆变器级的58）。 致动元件（80，71）可帮助从所述第二电源电压到地的中间节点（58）的切换; 限流晶体管（52，62）被布置在所述逆变器级，以限制流过的电流在开关期间，并减少了电路的功耗。

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