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    Improved sensing circuit for a semiconductor memory including bit line precharging and discharging functions
    1.
    发明公开
    Improved sensing circuit for a semiconductor memory including bit line precharging and discharging functions 审中-公开
    对于一个具有半导体存储器件的位线预充电和-Entladungsfunktionen提高读取装置

    公开(公告)号：EP1505605A1

    公开(公告)日：2005-02-09

    申请号：EP03017939.4

    申请日：2003-08-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vimercati, Daniele ,  Fiorina, Sara ,  Bolandrina, Efrem ,  Schippers, Stefan ,  Onorato, Marco

    IPC: G11C7/06 ,  G11C7/12 ,  G11C16/28 ,  G11C16/24

    CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C16/24 ,  G11C16/28

    Abstract: A sensing circuit (101;301) for a semiconductor memory comprising a circuit branch (109;309) intended to be electrically coupled to a memory bit line (BL) having connected thereto a memory cell (MC) to be sensed. A bit line precharge circuit (117;317) is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit (117;317) is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop (119,N4;327,R), for controlling the memory bit line potential during the precharge phase. A same circuit element (119;327,R) is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.

    Abstract translation: 一种用于半导体存储器，其包括一电路支路（109; 309）;感测电路（301 101），用于被电耦合到存储器的位线（BL），其具有与其连接的存储单元（MC）将被感测。 位线预充电电路（117; 317）被提供，用于预充电的存储器的位线到预定电势中的存储器单元的感测操作的预充电阶段。 评估电路（117; 317）与所述存储器的位线相关联，用于在存储单元感测操作的评估阶段期间电量在存储器位线的发展评价; 电量没有开发出在存储器位线指示所述存储器单元中的信息内容。 位线预充电电路是angepasst到两个充电和放电的存储位线，所以DASS模具预定到达位线电位无关的存储器位线的初始电位的预充电阶段的开始。 位线预充电电路是angepasst到两个充电和放电的存储位线，这取决于存储器位线电位和预定位线电位之间的差。 至少所述预充电电路包括：预充电的负反馈控制环（119，N4，327，R），用于在预充电阶段控制所述存储器位线电位。 同一电路元件;设置（119 327，R）预充电阶段期间没有控制存储器位线电位，并在该存储单元读出操作的评估阶段评估电量。

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