公开(公告)号：EP0926731A1

公开(公告)日：1999-06-30

申请号：EP97830685.0

申请日：1997-12-18

Applicant: STMicroelectronics S.r.l.

Inventor： Locati, Vanda ,  Clemente, Gino

IPC: H01L23/31 ,  H01L21/316

CPC classification number: H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31612 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Process for passivating an integrated circuit, providing for the formation on a top surface of the integrated circuit of at least a first layer of undoped oxide (5), characterized in that said first layer of undoped oxide (5) is formed by means of a chemical vapor deposition process performed at a pressure suitable for causing said first undoped oxide layer to substantially completely fill hollow regions between projecting regions (2) of the top surface of the integrated circuit.

Abstract translation: 钝化集成电路的方法，提供在至少第一层未掺杂氧化物（5）的集成电路的顶表面上的形成，其特征在于，所述第一层未掺杂的氧化物（5）通过 以适于使所述第一未掺杂氧化物层基本上完全填充所述集成电路的顶表面的突出区域（2）之间的中空区域的压力进行化学气相沉积工艺。

公开(公告)号：EP0893825A1

公开(公告)日：1999-01-27

申请号：EP97830383.2

申请日：1997-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： Locati, Vanda ,  Wurthwein, Arturo ,  Villa, Monica ,  Clemente, Gino ,  Lo Priore, Stefano

IPC: H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/31053 ,  H01L21/76224 ,  H01L21/76819

Abstract: A planarization method for improving the planarity of electronic devices integrated on a semiconductor substrate (1), which devices comprise a plurality of active elements formed with gate regions (2) which stand proud of the substrate (1) surface and define trench regions (3) therebetween. The method provides for the deposition, within said trench regions (3), of a dielectric stack structure comprising a first layer (4) of undoped oxide, a second layer (5) of oxide deposited over said first layer (4), and a third layer (6) of capping oxide. Also provided are two planarizing substeps consisting of a chemio-mechanical clearing substep followed by a dry etch-back substep to expose the top surfaces of said gate regions (2).

Abstract translation: 一种用于改善集成在半导体衬底（1）上的电子器件的平面度的平面化方法，该器件包括形成有栅极区域（2）的多个有源元件，所述栅极区域（2）以衬底（1）表面为傲，并且限定沟槽区域 ）。 该方法提供在所述沟槽区域（3）内沉积包括未掺杂氧化物的第一层（4），沉积在所述第一层（4）上的氧化物的第二层（5））的介电堆叠结构，以及 第三层（6）覆盖氧化物。 还提供了两个平坦化子步骤，其由化学机械清除子步骤，随后是干蚀刻子步骤，以暴露所述栅极区域（2）的顶表面。