公开(公告)号：EP0893825A1

公开(公告)日：1999-01-27

申请号：EP97830383.2

申请日：1997-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： Locati, Vanda ,  Wurthwein, Arturo ,  Villa, Monica ,  Clemente, Gino ,  Lo Priore, Stefano

IPC: H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/31053 ,  H01L21/76224 ,  H01L21/76819

Abstract: A planarization method for improving the planarity of electronic devices integrated on a semiconductor substrate (1), which devices comprise a plurality of active elements formed with gate regions (2) which stand proud of the substrate (1) surface and define trench regions (3) therebetween. The method provides for the deposition, within said trench regions (3), of a dielectric stack structure comprising a first layer (4) of undoped oxide, a second layer (5) of oxide deposited over said first layer (4), and a third layer (6) of capping oxide. Also provided are two planarizing substeps consisting of a chemio-mechanical clearing substep followed by a dry etch-back substep to expose the top surfaces of said gate regions (2).

Abstract translation: 一种用于改善集成在半导体衬底（1）上的电子器件的平面度的平面化方法，该器件包括形成有栅极区域（2）的多个有源元件，所述栅极区域（2）以衬底（1）表面为傲，并且限定沟槽区域 ）。 该方法提供在所述沟槽区域（3）内沉积包括未掺杂氧化物的第一层（4），沉积在所述第一层（4）上的氧化物的第二层（5））的介电堆叠结构，以及 第三层（6）覆盖氧化物。 还提供了两个平坦化子步骤，其由化学机械清除子步骤，随后是干蚀刻子步骤，以暴露所述栅极区域（2）的顶表面。