公开(公告)号：EP1231793A1

公开(公告)日：2002-08-14

申请号：EP01830084.8

申请日：2001-02-09

Applicant: STMicroelectronics S.r.l.

Inventor： Graziani, Andrea ,  Celetto, Luca ,  Alfonso, Daniele ,  Basso, Fabrizio ,  Cremonesi, Alessandro ,  Pau, Danilo

IPC: H04N7/26

CPC classification number: H04N19/40 ,  H04N19/90

Abstract: In order to generate, starting from an input MPEG bitstream (IS), an output MPEG bitstream (OS) having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream (IS), first portions and second portions are distinguished in the input bitstream (IS), which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream (IS) are subjected (104) to the required translation, then transferring (134) said first portions subjected to syntax and/or resolution translation to the output bitstream (OS). When the resolution is left unaltered, the second portions are transferred (138) from the input bitstream (IS) to the output bitstream (OS) in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream (IS) are subjected (108 to 130) to a filtering in the domain of the discrete cosine transform (DCT).

Abstract translation: 为了产生，从在输入MPEG位数据流（IS）开始输出MPEG位流（OS）具有至少一个实体选择中的语法，分辨率和比特率相对于输入比特流改性（IS），第一部分和第二 部分是在输入比特流（IS），分别，它们基本上不影响和做影响比特率的变化区别开来。 当语法和分辨率之间的至少一个要被修改，则输入比特流的（IS）的第一部分进行（104）到所需要的翻译，然后转移环（134）所述第一部分进行语法和/或分辨率 翻译到输出比特流（OS）。 当分辨率保持不变，第二部分从输入比特流（IS）在基本上不存在处理操作的输出位流（OS）转印（138）。 当分辨率改变时，输入比特流（IS）的所述第二部分进行（108至130），以过滤在所述离散余弦变换（DCT）的结构域。

公开(公告)号：EP0608664B1

公开(公告)日：1999-05-06

申请号：EP93830031.6

申请日：1993-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Golla, Carla ,  Cremonesi, Alessandro

IPC: H03H1/00 ,  H03H17/02

CPC classification number: H03H17/0286 ,  H03H17/02 ,  H03H2017/0247

公开(公告)号：EP1231794A1

公开(公告)日：2002-08-14

申请号：EP01830227.3

申请日：2001-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pau, Danilo ,  Alfonso, Daniele ,  Basso, Fabrizio ,  Piccinelli, Emiliano ,  Cremonesi, Alessandro

IPC: H04N7/26

CPC classification number: H04N19/59 ,  H04N19/40 ,  H04N19/48 ,  H04N19/90

Abstract: A process and a system for generating, starting from an MPEG input bitstream (IS), an MPEG output bitstream (OS), the output bitstream (OS) having a resolution (Hor/N x Vert/M) modified with respect to the resolution (Hor x Vert) of the input bitstream (IS). The process comprises the operations of:

distinguishing (100), in the input bitstream (IS), first portions and second portions which respectively substantially do not affect and do affect the variation of resolution; and
subjecting (114 to 122) said second portions of the input bitstream (IS) to a function of modification of the resolution obtained by filtration in the domain of the discrete cosine transform (DCT), and then transferring (134), to said output bitstream (OS), said second portions subjected to filtering in the domain of the discrete cosine transform.

The invention also relates to the corresponding computer program product.

Abstract translation: 用于从MPEG输入比特流（IS），MPEG输出比特流（OS）开始生成具有相对于分辨率修改的分辨率（Hor / N×Vert / M）的输出比特流（OS）的处理和系统 （Hor×Vert）的输入比特流（IS）。 该过程包括以下操作：在输入比特流（IS）中区分（100）分别基本上不影响并且确实影响分辨率变化的第一部分和第二部分; 并且输入比特流（IS）的所述第二部分（114至122）具有通过在离散余弦变换（DCT）的域中通过滤波获得的分辨率的修改的功能，然后将（134）传送到所述输出 比特流（OS），所述第二部分在离散余弦变换的域中进行滤波。 本发明还涉及相应的计算机程序产品。

公开(公告)号：EP0690566B1

公开(公告)日：2001-10-04

申请号：EP94830322.7

申请日：1994-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Dalle Feste, Sandro ,  Bianchesi, Marco ,  Cremonesi, Alessandro

IPC: H03H1/00 ,  H03H17/06 ,  H03H17/02

CPC classification number: H03H17/0226 ,  H03H17/0621

公开(公告)号：EP1324191A1

公开(公告)日：2003-07-02

申请号：EP01830814.8

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Cremonesi, Alessandro ,  Rovati, Fabrizio ,  Pau, Danilo

IPC: G06F9/318

CPC classification number: G06F9/30196 ,  G06F9/30181 ,  G06F9/30189

Abstract: A processing architecture enables execution of one first set of instructions (OsTask1.1, OsTask1.2, ...) and one second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...) compiled for being executed by two different CPUs, the first set of instructions (OsTask1.1, OsTask1.2, ...) not being executable by the second CPU, and the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...) not being executable by the first CPU. The architecture comprises a single CPU (CPU3) configured for executing both the instructions of the first set (OsTask1.1, OsTask1.2, ...) and the instructions of the second set (MmTask2.1, MmTask2.2, MmTask2.3, ...). The single CPU in question (CPU3) being selectively switchable between a first operating mode, in which the single CPU (CPU3) executes the first set instructions (OsTask1.1, OsTask1.2, ...), and a second operating mode, in which the single CPU (CPU3) executes the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...). The single processor (CPU3) is configured for recognizing a switching instruction between the first operating mode and the second operating mode and for switching between the first operating mode and the second operating mode according to the switching instruction. The solution can be generalized to the use of a number of switching instructions between more than two execution modes for different CPUs.

Abstract translation: 一种处理架构使得能够执行一组第一组指令（OsTask1.1，OsTask1.2，...）和一组第二组指令（MmTask2.1，MmTask2.2，MmTask2.3，...） 由两个不同的CPU执行，第一组指令（OsTask1.1，OsTask1.2，...）不能由第二个CPU执行，第二组指令（MmTask2.1，MmTask2.2，MmTask2.3 ，...）不能由第一个CPU执行。 该架构包括被配置为执行第一组（OsTask1.1，OsTask1.2，...）的指令和第二组的指令（MmTask2.1，MmTask2.2，MmTask2）的单个CPU（CPU3）。 3，...）。 所讨论的单个CPU（CPU3）可以在单CPU（CPU3）执行第一组指令（OsTask1.1，OsTask1.2，...）的第一操作模式和第二操作模式之间切换， 其中单个CPU（CPU3）执行第二组指令（MmTask2.1，MmTask2.2，MmTask2.3，...）。 单处理器（CPU3）被配置为根据切换指令识别第一操作模式和第二操作模式之间的切换指令，并且用于在第一操作模式和第二操作模式之间切换。 该解决方案可以推广到在不同CPU之间的两个以上执行模式之间使用多个切换指令。