公开(公告)号：EP1361541A1

公开(公告)日：2003-11-12

申请号：EP02425219.9

申请日：2002-04-09

Applicant: STMicroelectronics S.r.l.

Inventor： Rovati, Fabrizio ,  Gardella, Pierluigi

IPC: G06T7/20 ,  H04N5/14 ,  H04N7/26

CPC classification number: G06T7/223 ,  G06T2207/10016

Abstract: A process for realizing an estimate of global motion based on a sequence of subsequent video images, such as those received via an optical mouse (M) for the purposes of detecting its movement. Subsequent video images are represented by digital signals arranged in frames and for each estimate of a frame with respect to another, the procedure provides operations for:

choosing, from amongst a series of vectors originating from linear combinations of motion vectors resulting from estimates of previous frames and/or constant vectors, a vector considered as the best match for estimating the motion occurring between the two frames, the said selection operation in turn including the operations of:
performing a virtual overlay of the two frames to be compared (T 0 , T 0 -1) mutually offset both horizontally and vertically by amounts identified by the motion vector subjected to testing,
applying a selective grid of pixels to be subjected to testing,
calculating, for all pixels selected via the grid, a cost function to determine the effectiveness of the predictor, identifying the vector with the lowest cost function value as the best for the purposes of estimation.

公开(公告)号：EP1370086B1

公开(公告)日：2006-10-11

申请号：EP02425372.6

申请日：2002-06-07

Applicant: STMicroelectronics S.r.l.

Inventor： Alfonso, Daniele ,  Rovati, Fabrizio

IPC: H04N7/26

CPC classification number: H04N19/43 ,  H04N19/51 ,  H04N19/56

公开(公告)号：EP1324191A1

公开(公告)日：2003-07-02

申请号：EP01830814.8

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Cremonesi, Alessandro ,  Rovati, Fabrizio ,  Pau, Danilo

IPC: G06F9/318

CPC classification number: G06F9/30196 ,  G06F9/30181 ,  G06F9/30189

Abstract: A processing architecture enables execution of one first set of instructions (OsTask1.1, OsTask1.2, ...) and one second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...) compiled for being executed by two different CPUs, the first set of instructions (OsTask1.1, OsTask1.2, ...) not being executable by the second CPU, and the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...) not being executable by the first CPU. The architecture comprises a single CPU (CPU3) configured for executing both the instructions of the first set (OsTask1.1, OsTask1.2, ...) and the instructions of the second set (MmTask2.1, MmTask2.2, MmTask2.3, ...). The single CPU in question (CPU3) being selectively switchable between a first operating mode, in which the single CPU (CPU3) executes the first set instructions (OsTask1.1, OsTask1.2, ...), and a second operating mode, in which the single CPU (CPU3) executes the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...). The single processor (CPU3) is configured for recognizing a switching instruction between the first operating mode and the second operating mode and for switching between the first operating mode and the second operating mode according to the switching instruction. The solution can be generalized to the use of a number of switching instructions between more than two execution modes for different CPUs.

Abstract translation: 一种处理架构使得能够执行一组第一组指令（OsTask1.1，OsTask1.2，...）和一组第二组指令（MmTask2.1，MmTask2.2，MmTask2.3，...） 由两个不同的CPU执行，第一组指令（OsTask1.1，OsTask1.2，...）不能由第二个CPU执行，第二组指令（MmTask2.1，MmTask2.2，MmTask2.3 ，...）不能由第一个CPU执行。 该架构包括被配置为执行第一组（OsTask1.1，OsTask1.2，...）的指令和第二组的指令（MmTask2.1，MmTask2.2，MmTask2）的单个CPU（CPU3）。 3，...）。 所讨论的单个CPU（CPU3）可以在单CPU（CPU3）执行第一组指令（OsTask1.1，OsTask1.2，...）的第一操作模式和第二操作模式之间切换， 其中单个CPU（CPU3）执行第二组指令（MmTask2.1，MmTask2.2，MmTask2.3，...）。 单处理器（CPU3）被配置为根据切换指令识别第一操作模式和第二操作模式之间的切换指令，并且用于在第一操作模式和第二操作模式之间切换。 该解决方案可以推广到在不同CPU之间的两个以上执行模式之间使用多个切换指令。

公开(公告)号：EP1189169A1

公开(公告)日：2002-03-20

申请号：EP00830604.5

申请日：2000-09-07

Applicant: STMicroelectronics S.r.l.

Inventor： Rovati, Fabrizio ,  Pau, Danilo ,  Fanucci, Luca ,  Saponara, Sergio ,  Cenciotti, Andrea ,  Alfonso, Daniele

IPC: G06T7/20

CPC classification number: G06T7/238 ,  G06T2207/10016

Abstract: The architecture (10), which is adapted to be implemented in the form of a reusable IP cell, preferably comprises:

a motion estimation engine (16), configured to process a cost function (SAD, MAD, MSE) and identify a motion vector (MV) which minimizes this,
an internal memory (17) configured to store the sets of initial candidate vectors for the blocks of a reference frame;
first (18) and second (19) controllers to manage the motion vectors and manage an external frame memory (13);
a reference synchronizer (20) to align, at the input to the estimation engine (16), the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller (19), and
a control unit (21) for timing the units (16 to 20) included in the architecture (10) and the external interfacing of the architecture itself.

Preferred application to codec units operating according to standard MPEG/H.263.

Abstract translation: 适于以可重用IP小区的形式实现的架构（10）优选地包括：运动估计引擎（16），其被配置为处理成本函数（SAD，MAD，MSE）并且识别运动矢量 （MV），其使内存最小化;内部存储器（17），其被配置为存储用于参考帧的块的初始候选矢量集合; 第一（18）和第二（19）控制器来管理运动矢量并管理外部帧存储器（13）; 参考同步器（20），用于在估计引擎（16）的输入处将与参考块相关的数据与来自第二控制器（19）的候选块相关的数据对准;以及控制单元（21） 用于对包含在架构（10）中的单元（16至20）和架构本身的外部接口进行定时。 对根据标准MPEG / H.263运行的编解码器单元的首选应用。

公开(公告)号：EP0917362A1

公开(公告)日：1999-05-19

申请号：EP97830591.0

申请日：1997-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Pau, Danilo ,  Rovati, Fabrizio ,  Valsasna, Anna ,  Bruni, Roberta

IPC: H04N7/00

CPC classification number: H04N19/436 ,  H04N19/14 ,  H04N19/176 ,  H04N19/42 ,  H04N19/61

Abstract: A hardware accelerator of the estimation of the variance for a coding system of pictures composed of an array of lines and columns of pixels calculates the variance of macroblocks of a digitized video image for using the results for a real-time coding of the current image together with the preceding and successive images according to the video algorithm MPEG-2. The disclosed architecture minimizes the silicon area needed for implementing the hardware accelerator for a cost-effective reduction of the burden on the CPU of the system.
The use of a plurality of distinct filter/demultiplexers of known architectures is eliminated by conveying the incoming pixels to the respective input lines of distinct variance calculation paths by the use of a simple counter.

Abstract translation: 估计由像素的行和列的阵列组成的图像的编码系统的方差的硬件加速器计算数字化视频图像的宏块的方差，以便使用结果一起实时编码当前图像 与根据视频算法MPEG-2的先前和后续图像进行比较。 所公开的结构使实现硬件加速器所需的硅面积最小化，以便经济有效地减少系统的CPU负担。 通过使用简单的计数器将输入像素传送到不同方差计算路径的相应输入线，从而消除使用已知架构的多个不同滤波器/多路分离器。

公开(公告)号：EP1152621A1

公开(公告)日：2001-11-07

申请号：EP00830332.3

申请日：2000-05-05

Applicant: STMicroelectronics S.r.l.

Inventor： Pau, Danilo ,  Piccinelli, Emiliano ,  Rovati, Fabrizio

IPC: H04N7/26 ,  H04N7/36 ,  H04N5/14

CPC classification number: H04N5/145 ,  H04N19/51 ,  H04N19/56

Abstract: Motion estimation in video signals (10) organized in successive frames divided into macroblocks is carried out by means of the identification of motion vectors. In a first identification phase, starting from a current motion vector, a best motion vector predictor is identified, being chosen from a set of candidates. The best predictor thus identified is then subjected to a second refining phase. The aforesaid set of candidates is identified by selecting vectors belonging to macroblocks close to the said current vector within the current frame and the preceding frame. Preferably, the refining phase comprises the definition of a grid of n points centred on the central position to which the best motion vector points and the distance of the points of the grid from the said centre is defined as a function of the matching error (typically consisting of an SAD function) defined in the first identification phase. Application to the IPB and APM operating modes of the H.263+ video standard is envisaged.

Abstract translation: 通过运动矢量的识别来执行以划分为宏块的连续帧中组织的视频信号（10）中的运动估计。 在从当前运动矢量开始的第一识别阶段中，从一组候选中选出最佳运动矢量预测器。 然后将如此确定的最佳预测因子进行第二精炼阶段。 通过选择属于当前帧和前一帧中的当前向量附近的宏块的矢量来识别上述候选集。 优选地，精炼阶段包括以中心位置为中心的n个点的网格的定义，其中最佳运动向量点和网格的点与所述中心的距离被定义为匹配误差的函数（通常 由SAD功能组成）在第一个识别阶段中定义。 设想了对H.263 +视频标准的IPB和APM操作模式的应用。

公开(公告)号：EP1139669A1

公开(公告)日：2001-10-04

申请号：EP00106589.5

申请日：2000-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Rovati, Fabrizio ,  Pau, Danilo ,  Piccinelli, Emiliano

IPC: H04N7/26

CPC classification number: H04N19/53 ,  H04N19/433

Abstract: A coprocessor circuit for processing image data in digital form, including:

a motion vector controller block (10) for generating, starting from said image data, motion vector (MV) values including predictor data and macroblock data relating to a current macroblock of said image data to be estimated, said prediction data and macroblock data being adapted to be stored at respective memory addresses,
an address generator block (101) for extracting said respective addresses from said motion vector (MV) values,
a predictor fetch block (102) for retrieving said predictor data based on respective addresses extracted by said address generator block (101),
a current macroblock fetch and distengine block (104) for retrieving said macroblock data based on respective addresses extracted by said address generator block (10) and for processing said macroblock data according to a given function, and
a decision block (105) for collecting said retrieved data as partial results and selecting the best result therefrom.

Abstract translation: 一种用于处理数字形式的图像数据的协处理器电路，包括：运动矢量控制器块（10），用于从所述图像数据开始，生成包括与所述图像的当前宏块相关的预测数据和宏块数据的运动矢量（MV）值 要估计的数据，所述预测数据和宏块数据适于存储在相应存储器地址处，用于从所述运动矢量（MV）值提取所述各个地址的地址生成器块（101），用于 基于由所述地址生成器块（101）提取的相应地址，根据由所述地址生成器块（10）提取的相应地址来检索所述宏块数据的当前宏块获取和分发发送块（104）来检索所述预测器数据，并处理所述 根据给定功能的宏块数据，以及用于将所述检索到的数据作为部分结果收集并选择最佳值的判定块（105） 从它那里。

公开(公告)号：EP1134981A1

公开(公告)日：2001-09-19

申请号：EP00830200.2

申请日：2000-03-17

Applicant: STMicroelectronics S.r.l.

Inventor： Piccinelli, Emiliano ,  Rovati, Fabrizio ,  Pau, Danilo

IPC: H04N7/26

CPC classification number: H04N19/57 ,  H04N19/137 ,  H04N19/51

Abstract: A method of estimating the motion field of a digital picture sequence comprises subdividing a current picture to examine in an integer number of macroblocks, for each macroblock of the current picture determining a search window centered on a macroblock of a preceding picture placed in the same position of the considered macroblock of the current picture, carrying out a motion estimation between the considered macroblock of the current picture and the macroblock most similar to it included in the window. At least a dimension of the search window is established in function of the corresponding dimension of the search window used for the preceding picture, the estimated motion field of the preceding picture and certain threshold values.

Abstract translation: 估计数字图像序列的运动场的方法包括细分当前图像以检查整数个宏块，对于当前图像的每个宏块，确定以位于相同位置的前一图像的宏块为中心的搜索窗口 当前图像的所考虑的宏块，执行当前图片的所考虑的宏块与包括在窗口中最类似的宏块之间的运动估计。 根据用于前一图像的搜索窗口的对应维度，前一图像的估计运动场和某些阈值来确定搜索窗口的至少维度。

公开(公告)号：EP1081959A1

公开(公告)日：2001-03-07

申请号：EP99830545.2

申请日：1999-09-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pau, Danilo ,  Pezzoni, Luca ,  Rovati, Fabrizio ,  Sirtori, Daniele

IPC: H04N7/26 ,  H04N7/36

CPC classification number: H04N19/105 ,  H04N19/112 ,  H04N19/137 ,  H04N19/85

Abstract: A method of recognizing a progressive or an interlaced content of video pictures during their processing in a coder, comprises the following operations on at least on one of the components (luminance or chrominance) of the video signal:

a) defining a macroblock belonging to a frame of the preceding picture having dimensions R*S pixels, a half of it (R/2)*S being placed on the Top field Tp and the other half on the Bottom field Bp ;
b) for the chosen component of the video signal, calculating a first pair of coefficients (COEFF_1, COEFF_2) equivalent to

the sum, extended to all the columns and to all the even row of said macroblock, of the absolute values of the differences among the values assumed by said component of the video signal in the pixels of the same column and of consecutive rows belonging to the Top semi-frame and Bottom semi-frame, respectively, and
the sum, extended to all the columns and to each fourth row of said macroblock, of the absolute values of the differences among the values assumed by said component of the video signal in the pixels of the same column and of consecutive rows of the same parity belonging to the Top semi-frame and Bottom semi-frame respectively;

c) verifying whether the first one of the coefficients of said pair is greater than or equal to a prefixed first real positive number of times (a) of the second coefficient, incrementing a first counter (CONT_1) at each positive verification;
d) incrementing a second counter (NUM_MACROBLOCK) at each macroblock so tested;
e) calculating for each row of each Top semi-frame a second pair of coefficients (COEFF_3, COEFF_4) equivalent to

for each row the sum, extended to all the columns of each semi-frame of the absolute values of the differences among the values assumed by said component of the video signal in pixels of the Bottom semi-frame of the preceding picture and of the Bottom semi-frame of the current picture, belonging to the row following the considered row and to the same column, and
the sum, extended to all the columns of each semi-frame of the absolute values of the differences among the values assumed by said component of the video signal in pixels of the same column and, respectively, of said row of the Top semi-frame of the preceding picture and the row following the considered row, belonging to the Bottom semi-frame of the current picture, respectively;

f) verifying whether the second coefficient of said second pair is grater than or equal to a second prefixed real positive number of times (β) the first coefficient of said second pair, incrementing a third counter (CONT_2) at each positive verification;
g) incrementing a fourth counter (NUM_RIGHE) at each row so tested;
verifying whether the content of the first counter (CONT_1) is greater than or equal to a third prefixed real positive number of times (γ) the content of second counter (NUM_MACROBLOCK) and whether, at the same time, the content of the third counter (CONT 2) is greater than or equal to a fourth prefixed real positive number of times (δ) the content of the fourth counter (NUM_RIGHE): if so, considerating the frame composed of said Top and Bottom semi-frame an interlaced one, if not a progressive one.

Abstract translation: 认识到他们的处理过程中的渐进或视频图像的隔行扫描内容在一个编码器的方法，包括在所述视频信号的分量（亮度或色度）的至少一个以下操作： - 定义属于一个宏块一个） 具有尺寸preceding-图象的帧R * S像素，它（R / 2）* S被放置在顶场Tp和另一半上底场bp的半; b）该视频信号的所选择的分量，计算中相当于之和的第一对系数（COEFF_1，COEFF_2），延伸到所有的列和所有的偶数行。所述宏块的，的差的绝对值的 由在同一列中的和分别属于顶半帧和底半帧，连续行的像素的视频信号的所述部件，并且总和假定的值，扩展到所有的列和每个第四行 说宏块由在同一列中的像素与分别属于顶半帧和底半帧中的相同奇偶性的连续行的视频信号的所述部件假设值之间的差的绝对值的值，的 ; c）是否验证所述系数的计算对大于或等于所述第二系数的时间（a）一种前缀第一实正数，递增在每个正验证一个第一计数器（CONT_1）中的第一个; D）在递增进行测试，从而每个宏块的第二计数器（NUM_MACROBLOCK）; e）计算为每个顶半帧的每行相当于第二对系数（COEFF_3，COEFF_4）每行的总和，扩展到的值之间的差的绝对值的每个半帧的所有列 由视频信号的所述部件在preceding-图片的底部半帧的像素与当前画面的底部半帧的假设，属于行继考虑行和同一列中，并且该和， 分别延伸到由所述视频信号的所述部件在同一列中的像素假设的值和，之间的差的绝对值的每个半帧的所有列，则preceding-的顶半帧的所述行的 画面和行继考虑行，属于当前画面，分别的底部半帧; F）验证是否所述第二对中的第二系数是磨碎器小于或等于的倍的第二前缀实正数（测试版）所述第二对的所述第一系数，递增在每个正验证一个第三计数器（CONT_2）; 克）在递增以便测试各行的第四计数器（NUM_RIGHE）; 验证是否（CONT_1）第一计数器的含量为大于或等于的倍的第三前缀正实数（伽马）第二计数器（NUM_MACROBLOCK）和无论的内容，同时，所述第三计数器的内容 （CONT 2）大于或等于次四分之一前缀正实数（增量）的第四计数器的内容（NUM_RIGHE）：如果是这样，considerating所述顶部和底部半帧构成的帧隔行之一， 如果没有一个渐进。

公开(公告)号：EP1081959B1

公开(公告)日：2007-11-14

申请号：EP99830545.2

申请日：1999-09-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pau, Danilo ,  Pezzoni, Luca ,  Rovati, Fabrizio ,  Sirtori, Daniele

IPC: H04N7/26 ,  H04N7/36

CPC classification number: H04N19/105 ,  H04N19/112 ,  H04N19/137 ,  H04N19/85