公开(公告)号：EP1253635A1

公开(公告)日：2002-10-30

申请号：EP01830267.9

申请日：2001-04-23

Applicant: STMicroelectronics S.r.l.

Inventor： Crivelli, Barbara ,  Alessandri, Mauro ,  Servalli, Giorgio ,  Maurelli, Alfonso

IPC: H01L21/8247 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L29/66825

Abstract: The present invention relates to a method for sealing a nonvolatile memory device, characterized in that to comprise the following steps of: a) defining a nonvolatile memory cell (20), being composed by the overlap of a tunnel oxide (3), of a floating gate (1), of an interpoly dielectric (2), and of a control gate (4); b) deposing a silicon oxide layer (11) by a CVD (Chemical Vapor Deposition) at a temperature lower than 1000 °C on said control gate (4); c) densifing said silicon oxide layer (11) by a further thermal treatment (13). (Figure 5).

Abstract translation: 非易失性存储器件的密封方法技术领域本发明涉及一种用于密封非易失性存储器件的方法，其特征在于包括以下步骤：a）限定由隧道氧化物（3）的重叠构成的非易失性存储单元（20） 互补电介质（2）和控制栅极（4）的浮栅（1）; b）通过CVD（化学气相沉积）在所述控制栅极（4）上在低于1000℃的温度下沉积氧化硅层（11）; c）通过进一步的热处理（13）使所述氧化硅层（11）致密化。 （图5）。

公开(公告)号：EP1333473A1

公开(公告)日：2003-08-06

申请号：EP02425044.1

申请日：2002-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Crivelli, Barbara ,  Alessandri, Mauro

IPC: H01L21/28 ,  H01L29/788

CPC classification number: H01L29/511 ,  H01L21/28273 ,  H01L21/3144

Abstract: The invention relates to a process for manufacturing an interpoly dielectric layer (2) for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer (2). The process begins with forming the tunnel oxide (3), and hence the amorphous or polycrystalline silicon layer (4), using conventional techniques. After the amorphous or polycrystalline silicon layer (4) is surface cleansed and passivated, the surface of the polycrystalline layer (4) is :nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, doesn't exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

Abstract translation: 本发明涉及一种用于制造具有间隔电介质层（2）的半导体器件的非易失性存储单元的多层介电层（2）的方法。 该过程开始于使用常规技术形成隧道氧化物（3），因此形成非晶或多晶硅层（4）。 在无定形或多晶硅层（4）被表面清洁和钝化之后，多晶层（4）的表面通过使用自由基氮直接氮化。 之后，通过CVD技术形成作为ONO层或单个硅层的多晶硅电介质。 可以在执行直接氮化步骤之前或之后立即执行用于限定浮动栅极的掩模。 通过组合氮氧化物层和随后的电介质获得的互聚电介质的等效电学厚度在ONO层或单硅层实施例中不超过130埃。

公开(公告)号：EP1324393B1

公开(公告)日：2008-04-09

申请号：EP02014408.5

申请日：2002-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Allessandri Mauro ,  Crivelli, Barbara ,  Zonca, Romina

IPC: H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

公开(公告)号：EP1324393A1

公开(公告)日：2003-07-02

申请号：EP02014408.5

申请日：2002-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Allessandri Mauro ,  Crivelli, Barbara ,  Zonca, Romina

IPC: H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: The invention is a process for manufacturing a non-volatile memory cell having at least one gate region (10), the process comprising the steps of:

depositing a first dielectric layer onto a semiconductor substrate;
depositing a first semiconductor layer (1) onto the first dielectric layer to form a floating gate region of the memory cell; and
defining said floating gate region of the memory cell in the first semiconductor layer (1).

Advantageously in the invention, the manufacturing process further includes the step of:

depositing a second dielectric layer (5) onto the first conductive layer (1), the dielectric layer (5) having a higher dielectric constant than 10.

Also disclosed is a memory cell, which is integrated in a semiconductor substrate and has a gate region (10) that comprises a dielectric layer (5) formed over a first conductive layer (1) and having a higher dielectric constant than 10.

Abstract translation: 本发明是一种用于制造具有至少一个栅极区的非易失性存储单元（10）上的方法，该方法包括以下步骤：沉积到半导体衬底的第一介电层; 到第一电介质层上沉积第一半导体层（1），以形成该存储单元的浮置栅极区域; 和限定在第一半导体层（1）在存储单元的所述浮置栅区。 有利地，在本发明中，制造过程还包括以下步骤：沉积一第二介电层于10所以盘游离缺失（5），其具有（5）到第一导电层（1），所述介电层更高的介电常数的存储器 集成在一个半导体衬底，具有（10）做了栅极区细胞，在所有包括介电层（5）形成在第一导电层（1）和具有大于10 更高的介电常数