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    Phase change memory cell and manufacturing method thereof using minitrenches
    2.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    Phasenwechsel-Speicherzelle sowie deren Herstellungsverfahren手套Minigräben

    公开(公告)号：EP1339110A1

    公开(公告)日：2003-08-27

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一尺寸的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一薄部分（22）和第二薄部分（38a）直接电接触并限定亚光刻延伸部分的接触区域（58）。 第二薄部分（38a）由限定光刻开口（51）的模制层（49）围绕的氧化物间隔部分（55a）横向限定。 间隔物部分（55a）通过间隔物形成技术在形成光刻开口之后形成。

    Removable data storage device and related assembling method
    6.
    发明公开
    Removable data storage device and related assembling method 审中-公开
    Entfernbare Datenspeichervorrichtung undzugehörigesMontageverfahren

    公开(公告)号：EP1689217A1

    公开(公告)日：2006-08-09

    申请号：EP06001378.6

    申请日：2006-01-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Roveda, Marco ,  Villa, Davide ,  Zonca, Romina ,  Ghezzi, Stefano ,  Saltutti, Stefano ,  Costanzo, Luigi

    IPC: H05K5/02

    CPC classification number: H05K5/026

    Abstract: A removable storage device is described comprising at least one substrate (1) whereon a plurality of components (2, 3) are arranged. Advantageously, the removable storage device (10) comprises a casing (4) of the package type suitable to completely cover these components (2, 3) and to form, together with the substrate (1), an external coating of the removable storage device (10).
    Moreover, a method is described for assembling at least one removable storage device (10) thus realised.

    Abstract translation: 描述了一种可移动存储装置，其包括布置有多个部件（2,3）的至少一个基板（1）。 有利地，可移除存储装置（10）包括适合于完全覆盖这些部件（2,3）并与衬底（1）一起形成可拆卸存储装置的外部涂层的封装类型的壳体（4） （10）。 此外，描述了用于组装由此实现的至少一个可移动存储设备（10）的方法。

    Manufacturing process of a semiconductor non-volatile memory cell and corresponding memory-cell
    7.
    发明公开
    Manufacturing process of a semiconductor non-volatile memory cell and corresponding memory-cell 有权
    一种用于制造非易失性存储器单元和相应的存储单元的方法

    公开(公告)号：EP1324393A1

    公开(公告)日：2003-07-02

    申请号：EP02014408.5

    申请日：2002-06-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Allessandri Mauro ,  Crivelli, Barbara ,  Zonca, Romina

    IPC: H01L29/51

    CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    Abstract: The invention is a process for manufacturing a non-volatile memory cell having at least one gate region (10), the process comprising the steps of:

    depositing a first dielectric layer onto a semiconductor substrate;
    depositing a first semiconductor layer (1) onto the first dielectric layer to form a floating gate region of the memory cell; and
    defining said floating gate region of the memory cell in the first semiconductor layer (1).

    Advantageously in the invention, the manufacturing process further includes the step of:

    depositing a second dielectric layer (5) onto the first conductive layer (1), the dielectric layer (5) having a higher dielectric constant than 10.

    Also disclosed is a memory cell, which is integrated in a semiconductor substrate and has a gate region (10) that comprises a dielectric layer (5) formed over a first conductive layer (1) and having a higher dielectric constant than 10.

    Abstract translation: 本发明是一种用于制造具有至少一个栅极区的非易失性存储单元（10）上的方法，该方法包括以下步骤：沉积到半导体衬底的第一介电层; 到第一电介质层上沉积第一半导体层（1），以形成该存储单元的浮置栅极区域; 和限定在第一半导体层（1）在存储单元的所述浮置栅区。 有利地，在本发明中，制造过程还包括以下步骤：沉积一第二介电层于10所以盘游离缺失（5），其具有（5）到第一导电层（1），所述介电层更高的介电常数的存储器 集成在一个半导体衬底，具有（10）做了栅极区细胞，在所有包括介电层（5）形成在第一导电层（1）和具有大于10 更高的介电常数

    Small area contact region, high efficiency phase change memory cell and fabrication method thereof
    8.
    发明公开
    Small area contact region, high efficiency phase change memory cell and fabrication method thereof 审中-公开
    小面积接触区域，高效率相变存储器元件及其制造方法

    公开(公告)号：EP1318552A1

    公开(公告)日：2003-06-11

    申请号：EP01128461.9

    申请日：2001-12-05

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Riva, Caterina ,  Zonca, Romina

    IPC: H01L45/00 ,  G11C11/34 ,  H01L27/24

    CPC classification number: G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

    Abstract: A contact structure (30) in an electronic semiconductor device, including a first conducting region (31) having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region (32) having a second thin portion (32a) with a second sublithographic dimension in a second direction transverse to said first direction; the first and second conducting regions being in direct electrical contact at the first and second thin portions and defining a contact area (33) having a sublithografic extension, lower than 100 nm, preferably about 20 nm. The thin sublithographic portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer (34); the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic hard mask opening that is used to etch a mold opening (40) in a mold layer (38) and filling the mold opening.

    Abstract translation: 在半导体电子器件，其包括具有在第一方向上的第一亚光刻尺寸的第一薄壁部的第一导电区域（31）的接触结构（30）; 具有在第二方向上横向于所述第一方向的第二亚光刻尺寸的第二薄壁部（32A）的第二导电区（32）; 第一和第二导电区域在所述第一和第二薄膜部分直接电接触和限定具有sublithografic延伸的接触区域（33），低于100nm，优选约20nm。薄亚光刻的部分获得使用沉积代替 光刻的：所述第一薄壁部的设置于在第一电介质层（34）中的开口的壁; 所述第二薄壁部是通过在第一划界层的垂直壁罢免牺牲区域，在所述牺牲区域的自由侧罢免第二划界层，去除牺牲区域以形成亚光刻硬掩模开口获得并用于蚀刻 在模制层（38）和填充所述模具开口的模具开口（40）。

    Process for forming a thin film of TiSiN, in particular for phase change memory devices
    10.
    发明公开
    Process for forming a thin film of TiSiN, in particular for phase change memory devices 有权
    HerstellungdünnerSchichten aus TiSiN，besondersfürPhasenwechselspeicher

    公开(公告)号：EP1482551A1

    公开(公告)日：2004-12-01

    申请号：EP03425337.7

    申请日：2003-05-26

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Zonca, Romina

    IPC: H01L21/768

    CPC classification number: H01L45/06 ,  H01L21/76841 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

    Abstract: The process for forming a film of TiSiN includes the following sequence of steps: deposition of a TiN film at medium temperature, for example, 300-450°C, by thermal decomposition of a metallorganic precursor, for example TDMAT (Tetrakis Dimethylamino Titanium); exposition to a silicon releasing gas, such as silane (SiH 4 ) and dichlorine-silane (SiH 2 Cl 2 ) at 10-90 sccm -standard cube centimeters per minute- for a quite long time, for example, longer than 10 s but less than 90 s, preferably about 40 s; exposition to a H 2 /N 2 plasma at 200-800 sccm, for 10-90 s, preferably about 40 s.

    Abstract translation: 制备钛，硅和氮（TiSiN）络合物的膜包括：（a）沉积TiN（钛氮）膜; 和（b）将钛和氮复合物（TiN）的膜暴露于硅释放气体，而不预先将膜暴露于碳还原处理。

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