公开(公告)号：EP0809286B1

公开(公告)日：2003-10-01

申请号：EP96830280.2

申请日：1996-05-14

Applicant: STMicroelectronics S.r.l.

Inventor： Palmieri, Michele ,  Galbiati, Paola ,  Vecchi, Lodovica

IPC: H01L21/8249 ,  H01L21/74

CPC classification number: H01L21/266 ,  H01L21/74 ,  H01L21/8249

公开(公告)号：EP1158583A1

公开(公告)日：2001-11-28

申请号：EP00830373.7

申请日：2000-05-23

Applicant: STMicroelectronics S.r.l.

Inventor： Croce, Giuseppe ,  Moscatelli, Alessandro ,  Merlini, Alessandra ,  Galbiati, Paola

IPC: H01L29/78 ,  H01L29/417

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456

Abstract: An LDMOS structure is realized in a region of a first type of conductivity (N-POCKET) of a semiconductor substrate and comprises a gate, a drain region and a source region, the latter being constituted by a body diffusion (PBODY) of a second type of conductivity within said first region (N-POCKET), a source diffusion (N + ) of said first type of conductivity within said body diffusion (PBODY); an electrical connection diffusion (P + ) of said second type of conductivity, in a limited area of said source region, extending through said source diffusion (N + ) and reaching down to said body diffusion (PBODY), at least a source contact on said source diffusion (N + ) and said electrical connection diffusion (P + ), and further comprises a layer of silicide over the whole area of the source region short-circuiting said source diffusion (N + ) and said electrical connection diffusion (P + ); said source contact being established on said silicide layer.

Abstract translation: LDMOS结构在半导体衬底的第一导电类型（N-POCKET）的区域中实现并且包括栅极，漏极区域和源极区域，后者由第二导电类型的体扩散（PBODY） 所述第一区域内的导电类型（N-POCKET），所述体扩散（PBODY）内所述第一导电类型的源极扩散（N +）; 在所述源极区域的有限区域中的所述第二类型导电性的电连接扩散（P +）延伸穿过所述源极扩散（N +）并到达所述体扩散（PBODY），所述源极上的至少源极接触 扩散（N +）和所述电连接扩散（P +），并且还包括在源区的整个区域上短路所述源扩散（N +）和所述电连接扩散（P +）的硅化物层; 所述源极触点建立在所述硅化物层上。

公开(公告)号：EP0731504B1

公开(公告)日：2002-11-27

申请号：EP95830088.1

申请日：1995-03-09

Applicant: STMicroelectronics S.r.l.

Inventor： Contiero, Claudio ,  Galbiati, Paola ,  Palmieri, Michele

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/8247 ,  H01L21/265 ,  H01L27/06 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/823456 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0847 ,  H01L29/66674 ,  H01L29/7816

Abstract: A process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells provides for: forming respective laterally displaced isolated semiconductor regions (R1,R2,R6), electrically insulated from each other and from a common semiconductor substrate (1), inside which the devices will be formed; forming conductive insulated gate regions (33,34,37) for the lateral DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions (R1,R2,R6); inside the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, forming deep body regions (25,26) aligned with edges of the insulated gate regions (33,34), and channel regions (29,30) extending under the insulated gate regions (33,34). The deep body regions (25,26) are formed by means of a first implantation of a first dopant in a direction substantially orthogonal to a top surface of the integrated circuit, performed with an energy and with a dopant dose such that the concentration of the first dopant has a peak located at a prescribed distance from the surface of the isolated semiconductor regions (R1,R2). The channel regions (29,30) are formed by means of a second implantation of a second dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that said channel regions (29,30) are formed directly after the implantation of the second dopant without performing a thermal diffusion at a high temperature of the second dopant.

公开(公告)号：EP0730309B1

公开(公告)日：1998-10-14

申请号：EP95830045.1

申请日：1995-02-21

Applicant: STMicroelectronics S.r.l.

Inventor： De Petro, Riccardo ,  Palmieri, Michele ,  Galbiati, Paola ,  Contiero, Claudio

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific resistivity RDS on enriched drain regions (16) are formed by implanting doping material (N) in the silicon through apertures in the field oxide (11) obtained with a selective anisotropic etching by utilising as a mask the strips of polycrystaline silicon (14) which serve as gate electrodes and field electrodes.

公开(公告)号：EP1148555A1

公开(公告)日：2001-10-24

申请号：EP00830308.3

申请日：2000-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Croce, Giuseppe ,  Moscatelli, Alessandro ,  Merlini, Alessandra ,  Galbiati, Paola

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/08

CPC classification number: H01L29/0878 ,  H01L29/7816

Abstract: A RESURF LDMOS integrated structure realized in a first region (drain well) of a first type of conductivity defined in a semiconductor substrate of opposite type of conductivity and comprising a source region of said first type of conductivity formed in a body region of said opposite type of conductivity. Said body region is contained within a surface portion (body buffer region) of the first region that is more heavily doped than the rest of the region to avoid punch-through when the structure operates as a high side driver.

Abstract translation: RESURF LDMOS集成结构，其实现于在相反导电类型的半导体衬底中限定的第一类型导电体的第一区域（漏极阱）中，并且包括形成在所述相反类型的体区域中的所述第一类型的导电源的源极区域 的电导率。 所述体区域包含在比其余区域更重掺杂的第一区域的表面部分（体缓冲区域）中，以避免当该结构作为高侧驱动器时起作用。

公开(公告)号：EP0685891B1

公开(公告)日：2001-08-08

申请号：EP94830266.6

申请日：1994-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Galbiati, Paola ,  Mastromatteo, Ubaldo

IPC: H01L29/861

CPC classification number: H01L29/66128 ,  H01L29/8611