公开(公告)号：EP1071211A1

公开(公告)日：2001-01-24

申请号：EP99830467.9

申请日：1999-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Disegni, Fabio ,  Dima, Vincenzo ,  Bartoli, Simone

IPC: H03K17/06 ,  H03K17/30

CPC classification number: H03K17/063 ,  H03K19/0027

Abstract: The present invention refers to a circuit disposal of a transistor shaped like a diode, in particular to a disposal able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal.
In an embodiment the circuit disposal comprises a first pMOS transistor (300) having a second pMOS transistor (301) shaped like a diode connected between the gate and the drain of the first transistor and a current generator (310) connected to the gates of the two transistors. Such a circuitry disposal it is also applicable to a nMOS transistor. From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series to the gate that provides an opportune delta of voltage.

Abstract translation: 本发明涉及一种形状类似二极管的晶体管的电路处理，特别是涉及能够降低晶体管的阈值电压并等于电路处置中所用晶体管的阈值电压差的处理。 在一个实施例中，电路处理包括具有第二pMOS晶体管（301）的第一pMOS晶体管（300），第二pMOS晶体管（301）形成为类似于连接在第一晶体管的栅极和漏极之间的二极管，以及电流发生器（310） 两个晶体管。 这种电路处理也适用于nMOS晶体管。 从一般观点来看，本发明涉及通过使用串联提供电压的时间增量的电路的栅极电压增加（对于nMOS晶体管）或降低（对于pMOS晶体管）的nMOS或pMOS晶体管， 。

公开(公告)号：EP1071211B1

公开(公告)日：2006-09-13

申请号：EP99830467.9

申请日：1999-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Disegni, Fabio ,  Dima, Vincenzo ,  Bartoli, Simone

IPC: H03K17/06 ,  H03K17/30

CPC classification number: H03K17/063 ,  H03K19/0027