公开(公告)号：EP0905704B1

公开(公告)日：2010-03-31

申请号：EP97830467.3

申请日：1997-09-24

Applicant: STMicroelectronics S.r.l.

Inventor： Bartoli, Simone ,  Dima, Vincenzo ,  Sali, Mauro Luigi

IPC: G11C8/00 ,  G11C16/06

CPC classification number: G11C8/12 ,  G11C16/08

公开(公告)号：EP1071211A1

公开(公告)日：2001-01-24

申请号：EP99830467.9

申请日：1999-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Disegni, Fabio ,  Dima, Vincenzo ,  Bartoli, Simone

IPC: H03K17/06 ,  H03K17/30

CPC classification number: H03K17/063 ,  H03K19/0027

Abstract: The present invention refers to a circuit disposal of a transistor shaped like a diode, in particular to a disposal able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal.
In an embodiment the circuit disposal comprises a first pMOS transistor (300) having a second pMOS transistor (301) shaped like a diode connected between the gate and the drain of the first transistor and a current generator (310) connected to the gates of the two transistors. Such a circuitry disposal it is also applicable to a nMOS transistor. From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series to the gate that provides an opportune delta of voltage.

Abstract translation: 本发明涉及一种形状类似二极管的晶体管的电路处理，特别是涉及能够降低晶体管的阈值电压并等于电路处置中所用晶体管的阈值电压差的处理。 在一个实施例中，电路处理包括具有第二pMOS晶体管（301）的第一pMOS晶体管（300），第二pMOS晶体管（301）形成为类似于连接在第一晶体管的栅极和漏极之间的二极管，以及电流发生器（310） 两个晶体管。 这种电路处理也适用于nMOS晶体管。 从一般观点来看，本发明涉及通过使用串联提供电压的时间增量的电路的栅极电压增加（对于nMOS晶体管）或降低（对于pMOS晶体管）的nMOS或pMOS晶体管， 。

公开(公告)号：EP1071211B1

公开(公告)日：2006-09-13

申请号：EP99830467.9

申请日：1999-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Disegni, Fabio ,  Dima, Vincenzo ,  Bartoli, Simone

IPC: H03K17/06 ,  H03K17/30

CPC classification number: H03K17/063 ,  H03K19/0027

公开(公告)号：EP1071094B1

公开(公告)日：2005-11-23

申请号：EP99830403.4

申请日：1999-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Dima, Vincenzo ,  Brani, Francesco ,  Defendi, Marco

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

公开(公告)号：EP1071094A1

公开(公告)日：2001-01-24

申请号：EP99830403.4

申请日：1999-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Dima, Vincenzo ,  Brani, Francesco ,  Defendi, Marco

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

Abstract: A circuit for reading a semiconductor memory device comprises at least one global circuit (1) for generating a global reference signal (RIFN) for a respective plurality of cell-reading circuits (SA1-SAn) disposed locally in the memory device. The circuit comprises at least one circuit (51-5an) for replicating the reference signal (RIFN) locally in order to generate a local reference signal (MAT11-MAT1n) to be supplied to at least one respective cell-reading circuit (SA1-SAn).

Abstract translation: 用于读取半导体存储器件的电路包括至少一个全局电路（1），用于为本地存储在存储器件中的多个单元读取电路（SA1-SAn）生成全局参考信号（RIFN）。 该电路包括用于本地复制参考信号（RIFN）的至少一个电路（51-5an），以便产生要提供给至少一个相应的单元读取电路（SA1-SAn）的本地参考信号（MAT11-MAT1n） ）。

公开(公告)号：EP0905704A1

公开(公告)日：1999-03-31

申请号：EP97830467.3

申请日：1997-09-24

Applicant: STMicroelectronics S.r.l.

Inventor： Bartoli, Simone ,  Dima, Vincenzo ,  Sali, Mauro Luigi

IPC: G11C8/00 ,  G11C16/06

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A memory device comprises a plurality of independent memory sectors, external address signal inputs (2) for receiving external address signals (A0-A17) for addressing individual memory locations of the memory device, the external address signals (A0-A17) comprising external memory sector address signals (A12-A17) allowing for individually addressing each memory sector, and a memory sector selection means (11) for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals (A12-A17). A first and a second alternative internal memory sector address signal paths (6,7) are provided for supplying the external memory sector address signals (A12-A17) to the memory sector selection means (11), the first path (6) providing no logic inversion and the second path (7) providing logic inversion. Programmable means (12) allows for activating either one or the other of the first and second internal memory sector address signal paths (6,7), so that a position of each memory sector in a space of values (00000h - 3FFFFh) of the external address signals (A0-A17) can be changed by activating either one or the other of the first and second internal memory sector address signal paths (6,7).

Abstract translation: 存储器件包括多个独立的存储器扇区，用于接收用于寻址存储器件的各个存储器位置的外部地址信号（A0-A17）的外部地址信号输入（2），包括外部存储器的外部地址信号（A0-A17） 允许单独寻址每个存储器扇区的扇区地址信号（A12-A17）和用于根据外部存储器扇区地址信号（A12-A17）的值来选择多个存储器扇区之一的存储器扇区选择装置（11） 。 提供第一和第二替代的内部存储器扇区地址信号路径（6,7），用于将外部存储器扇区地址信号（A12-A17）提供给存储器扇区选择装置（11），第一路径（6）不提供 逻辑反演和第二路径（7）提供逻辑反演。 可编程装置（12）允许激活第一和第二内部存储器扇区地址信号路径（6,7）中的一个或另一个，使得每个存储器扇区在空间中的位置（00000h-3FFFFh） 可以通过激活第一和第二内部存储器扇区地址信号路径（6,7）中的一个或另一个来改变外部地址信号（A0-A17）。