公开(公告)号：EP1047077A1

公开(公告)日：2000-10-25

申请号：EP99830236.8

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Commodaro, Stefano ,  Farina, Francesco

IPC: G11C8/00 ,  G11C16/06 ,  G11C7/18

CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C7/18 ,  G11C8/10

Abstract: The memory array (30) comprises a plurality of cells (50), grouped together in sectors (31) and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines (35) are connected to at least two word lines (36) in each sector (31), through local row decoders (33); global bit lines (42) are connected to at least two local bit lines (43) in each sector (31), through local column decoders (40). The global column decoder (41) is arranged in the centre of the memory array (30), and separates from each other an upper half (30a) and a lower half (30b) of the memory array (30). Sense amplifiers (47) are also arranged in the middle of the array, thus saving space. This architecture also provides lesser stress of the cells, better reliability, and better production performance. In addition, each sector (31) is completely disconnected from the remaining sectors, and only the faulty row or column of a single sector should be doubled.

Abstract translation: 闪存EEPROM存储器阵列（30）包括在扇区（31）中分组在一起的单元，并且具有分级行和分层列解码。 全局字线（35）通过本地行解码器（33）连接到每个扇区中的字线（36）。 全局位线（42）通过本地列解码器（40）连接到本地位线（43）。 全局列解码器（41）和读出放大器（47）将上半部分（30a）与存储器阵列的下半部分（30b）分开。