公开(公告)号：EP1418589A1

公开(公告)日：2004-05-12

申请号：EP02425676.0

申请日：2002-11-06

Applicant: STMicroelectronics S.r.l.

Inventor： Lisi, Carlo ,  Ferrario, Marco ,  Scotti, Massimiliano ,  Confalonieri, Emanuele

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/04

Abstract: Described herein is a device (20) for timing random reading of a memory device with a data access time (T A ), in which reading is performed by means of a succession of consecutive operations, the timing device (20) being designed to generate, for each operation, a corresponding timing signal (PS(i)) such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration (T F (i)), which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration (T F (i)); the sum of the fixed durations (T F (i)) being equal to the data access time (T A ) of the memory device.

Abstract translation: 这里描述了一种用于定时随机读取具有数据访问时间（TA）的存储器件的装置（20），其中通过一系列连续操作进行读取，所述定时装置（20）被设计成生成 对于每个操作，相应的定时信号（PS（i）），使得无论存储器件的操作条件如何，相应的操作持续相当于相应的固定持续时间（TF（i））的时间，哪个 被确定为保证在固定持续时间（TF（i））内存储器件的最差工作状态下的操作完成; 固定持续时间（TF（i））的总和等于存储器件的数据访问时间（TA）。

公开(公告)号：EP1686591B1

公开(公告)日：2008-01-09

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

公开(公告)号：EP1686591A1

公开(公告)日：2006-08-02

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

Abstract translation: 一种存储器装置（100）被提议。 所述存储器装置包括存储器单元的用于偏置一组选择的存储单元的多个（MC）每一个用于存储一个值，至少一个参考单元（先生0 -Mr 2），偏压装置（115）和所述至少一个 具有用于每个被选择的存储单元的电流（Ic，Ir）的各基准单元的检测的阈值的到达基本上单调时间图案，装置（130）的偏置电压（VC，VR）参考单元，和 装置（145），用于确定挖掘存储在每个选定存储器单元gemäß阈值的通过和所述至少一个参考单元的选定存储器单元的电流的到达的时间关系的值。 偏压装置包括用于将预定偏置电流（Ib），以所选择的存储器单元和所述至少一个参考蜂窝小区的装置（305）。

公开(公告)号：EP1653474A1

公开(公告)日：2006-05-03

申请号：EP05022651.3

申请日：2005-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele ,  Del Gatto, Nicola ,  Lisi, Carlo ,  Ferrario, Marco

IPC: G11C11/56 ,  G11C5/14 ,  G11C16/30

CPC classification number: G11C8/10 ,  G11C8/18 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621

Abstract: The present invention relates to a method for programming a multilevel memory of the flash EEPROM type comprising a matrix of cells grouped in memory words.
Advantageously according to the invention the method provides the simultaneous generation of a first programming voltage value (V PROG ) and a second verify voltage value (V VER ), suitable to bias word lines (WLS) of the above memory matrix, respectively during programming and verify operations of the memory itself.
The present invention also relates to a circuit implementing the above method.

Abstract translation: 本发明涉及一种用于编程闪存EEPROM类型的多级存储器的方法，包括分组在存储器字中的单元矩阵。 有利地，根据本发明，该方法提供了同时产生适于在编程期间偏置上述存储器矩阵的字线（WLS）的第一编程电压值（V PROG）和第二验证电压值（V VER），以及 验证内存本身的操作。 本发明还涉及实现上述方法的电路。