公开(公告)号：EP1434234A3

公开(公告)日：2009-03-25

申请号：EP03104713.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Mastroianni, Francesco ,  Scotti, Massimiliano ,  Geraci, Antonio ,  Pozzato, Andrea

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: A non-volatile memory device (103) suitable to be programmed in a sequential mode is proposed. The device includes a plurality of blocks of memory cells (121) each one for storing a word, each block being identified by an address, means (124) for loading an input address at the beginning of a programming procedure and means (136,142) for setting an internal address to the input address; the device further includes means (127) for loading a predetermined number of input words in succession, means (130-133) for latching a page consisting of the predetermined number of input words, means (145-157) for executing a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and means (139,142) for incrementing the internal address of the predetermined number in response to the completion of the programming operation.

公开(公告)号：EP1434234A2

公开(公告)日：2004-06-30

申请号：EP03104713.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Mastroianni, Francesco ,  Scotti, Massimiliano ,  Geraci, Antonio ,  Pozzato, Andrea

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: A non-volatile memory device (103) suitable to be programmed in a sequential mode is proposed. The device includes a plurality of blocks of memory cells (121) each one for storing a word, each block being identified by an address, means (124) for loading an input address at the beginning of a programming procedure and means (136,142) for setting an internal address to the input address; the device further includes means (127) for loading a predetermined number of input words in succession, means (130-133) for latching a page consisting of the predetermined number of input words, means (145-157) for executing a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and means (139,142) for incrementing the internal address of the predetermined number in response to the completion of the programming operation.

Abstract translation: 提出了一种适用于以顺序模式编程的非易失性存储器件（103）。 该装置包括多个存储单元块（121），每个存储单元块（121）用于存储单词，每个块由地址标识，用于在编程程序开始时加载输入地址的装置（124）和装置（136,142），用于 设置输入地址的内部地址; 该设备还包括用于连续加载预定数量的输入字的装置（127），用于锁存由预定数量的输入字组成的页面的装置（130-133），用于执行编程操作的装置（145-157），包括： 在由内部地址开始的由连续地址标识的块中写入页面，以及响应于编程操作的完成来增加预定数量的内部地址的装置（139,142）。

公开(公告)号：EP1418589A1

公开(公告)日：2004-05-12

申请号：EP02425676.0

申请日：2002-11-06

Applicant: STMicroelectronics S.r.l.

Inventor： Lisi, Carlo ,  Ferrario, Marco ,  Scotti, Massimiliano ,  Confalonieri, Emanuele

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/04

Abstract: Described herein is a device (20) for timing random reading of a memory device with a data access time (T A ), in which reading is performed by means of a succession of consecutive operations, the timing device (20) being designed to generate, for each operation, a corresponding timing signal (PS(i)) such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration (T F (i)), which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration (T F (i)); the sum of the fixed durations (T F (i)) being equal to the data access time (T A ) of the memory device.

Abstract translation: 这里描述了一种用于定时随机读取具有数据访问时间（TA）的存储器件的装置（20），其中通过一系列连续操作进行读取，所述定时装置（20）被设计成生成 对于每个操作，相应的定时信号（PS（i）），使得无论存储器件的操作条件如何，相应的操作持续相当于相应的固定持续时间（TF（i））的时间，哪个 被确定为保证在固定持续时间（TF（i））内存储器件的最差工作状态下的操作完成; 固定持续时间（TF（i））的总和等于存储器件的数据访问时间（TA）。

公开(公告)号：EP1646051B1

公开(公告)日：2008-03-05

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

公开(公告)号：EP1646051A1

公开(公告)日：2006-04-12

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

Abstract translation: 在存储装置（1; 30），其具有在（2）的存储单元（3）阵列，列解码器（9）被配置为处理存储单元（3），和一个电荷泵电源电路（6; 32 ）生成一个升压电源电压（V b;对列译码器（9）V年）。 和列译码器（9）;所述的连接阶段（22）的供电电路（32 6）之间布置; 连接阶段（22）的高阻抗状态和低阻抗状态之间切换，并且被配置为切换到高阻抗状态的存储装置（1; 30）的给定操作条件的读出期间，尤其是 一步。