公开(公告)号：EP1184873B1

公开(公告)日：2008-12-10

申请号：EP00830582.3

申请日：2000-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Geraci, Antonino ,  Lisi, Carlo ,  Bedarida, Lorenzo ,  Sforzin, Marco

IPC: G11C16/28 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C16/28

公开(公告)号：EP1653474A1

公开(公告)日：2006-05-03

申请号：EP05022651.3

申请日：2005-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele ,  Del Gatto, Nicola ,  Lisi, Carlo ,  Ferrario, Marco

IPC: G11C11/56 ,  G11C5/14 ,  G11C16/30

CPC classification number: G11C8/10 ,  G11C8/18 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621

Abstract: The present invention relates to a method for programming a multilevel memory of the flash EEPROM type comprising a matrix of cells grouped in memory words.
Advantageously according to the invention the method provides the simultaneous generation of a first programming voltage value (V PROG ) and a second verify voltage value (V VER ), suitable to bias word lines (WLS) of the above memory matrix, respectively during programming and verify operations of the memory itself.
The present invention also relates to a circuit implementing the above method.

Abstract translation: 本发明涉及一种用于编程闪存EEPROM类型的多级存储器的方法，包括分组在存储器字中的单元矩阵。 有利地，根据本发明，该方法提供了同时产生适于在编程期间偏置上述存储器矩阵的字线（WLS）的第一编程电压值（V PROG）和第二验证电压值（V VER），以及 验证内存本身的操作。 本发明还涉及实现上述方法的电路。

公开(公告)号：EP1418589A1

公开(公告)日：2004-05-12

申请号：EP02425676.0

申请日：2002-11-06

Applicant: STMicroelectronics S.r.l.

Inventor： Lisi, Carlo ,  Ferrario, Marco ,  Scotti, Massimiliano ,  Confalonieri, Emanuele

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/04

Abstract: Described herein is a device (20) for timing random reading of a memory device with a data access time (T A ), in which reading is performed by means of a succession of consecutive operations, the timing device (20) being designed to generate, for each operation, a corresponding timing signal (PS(i)) such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration (T F (i)), which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration (T F (i)); the sum of the fixed durations (T F (i)) being equal to the data access time (T A ) of the memory device.

Abstract translation: 这里描述了一种用于定时随机读取具有数据访问时间（TA）的存储器件的装置（20），其中通过一系列连续操作进行读取，所述定时装置（20）被设计成生成 对于每个操作，相应的定时信号（PS（i）），使得无论存储器件的操作条件如何，相应的操作持续相当于相应的固定持续时间（TF（i））的时间，哪个 被确定为保证在固定持续时间（TF（i））内存储器件的最差工作状态下的操作完成; 固定持续时间（TF（i））的总和等于存储器件的数据访问时间（TA）。

公开(公告)号：EP1184873A1

公开(公告)日：2002-03-06

申请号：EP00830582.3

申请日：2000-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Geraci, Antonino ,  Lisi, Carlo ,  Bedarida, Lorenzo ,  Sforzin, Marco

IPC: G11C16/28 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C16/28

Abstract: A direct-comparison reading circuit for a nonvolatile memory array (2) having a plurality of memory cells (4) arranged in rows and columns (9), and at least one bit line (7), includes at least one array line (13), selectively connectable to the bit line (7), and a reference line (14); a precharging circuit (17) for precharging the array line (13) and reference line (14) at a preset precharging potential (V PC ); at least one comparator (35) having a first terminal connected to the array line (13), and a second terminal connected to the reference line (14); and an equalization circuit (15, 23, 26) for equalizing the potentials of the array line (13) and reference line (14) in the precharging step. In addition, the reading circuit includes an equalization line (15) distinct from the reference line (14); and controlled switches (23, 26) for connecting, in the precharging step, the equalization line (15) to the array line (13) and to the reference line (14), and for disconnecting the equalization line (15) from the array line (13) and from the reference line (14) at the end of the precharging step.

Abstract translation: 一种用于具有以行和列（9）排列的多个存储单元（4）和至少一个位线（7）的非易失性存储器阵列（2）的直接比较读取电路，包括至少一个阵列线（13） ），可选择地连接到位线（7）和参考线（14）; 用于以预设的预充电电位（VPC）对阵列线（13）和参考线（14）进行预充电的预充电电路（17）; 至少一个具有连接到阵列线（13）的第一端子的比较器（35）和连接到参考线（14）的第二端子; 以及用于在预充电步骤中均衡阵列线（13）和参考线（14）的电位的均衡电路（15,23,26）。 另外，读取电路包括与参考线（14）不同的均衡线（15）。 和控制开关（23,26），用于在预充电步骤中将均衡线（15）连接到阵列线（13）和参考线（14），并将均衡线（15）与阵列 在预充电步骤结束时从线（13）和参考线（14）移动。