公开(公告)号：EP1505605A1

公开(公告)日：2005-02-09

申请号：EP03017939.4

申请日：2003-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Fiorina, Sara ,  Bolandrina, Efrem ,  Schippers, Stefan ,  Onorato, Marco

IPC: G11C7/06 ,  G11C7/12 ,  G11C16/28 ,  G11C16/24

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C16/24 ,  G11C16/28

Abstract: A sensing circuit (101;301) for a semiconductor memory comprising a circuit branch (109;309) intended to be electrically coupled to a memory bit line (BL) having connected thereto a memory cell (MC) to be sensed. A bit line precharge circuit (117;317) is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit (117;317) is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop (119,N4;327,R), for controlling the memory bit line potential during the precharge phase. A same circuit element (119;327,R) is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.

Abstract translation: 一种用于半导体存储器，其包括一电路支路（109; 309）;感测电路（301 101），用于被电耦合到存储器的位线（BL），其具有与其连接的存储单元（MC）将被感测。 位线预充电电路（117; 317）被提供，用于预充电的存储器的位线到预定电势中的存储器单元的感测操作的预充电阶段。 评估电路（117; 317）与所述存储器的位线相关联，用于在存储单元感测操作的评估阶段期间电量在存储器位线的发展评价; 电量没有开发出在存储器位线指示所述存储器单元中的信息内容。 位线预充电电路是angepasst到两个充电和放电的存储位线，所以DASS模具预定到达位线电位无关的存储器位线的初始电位的预充电阶段的开始。 位线预充电电路是angepasst到两个充电和放电的存储位线，这取决于存储器位线电位和预定位线电位之间的差。 至少所述预充电电路包括：预充电的负反馈控制环（119，N4，327，R），用于在预充电阶段控制所述存储器位线电位。 同一电路元件;设置（119 327，R）预充电阶段期间没有控制存储器位线电位，并在该存储单元读出操作的评估阶段评估电量。

公开(公告)号：EP1237279A1

公开(公告)日：2002-09-04

申请号：EP01830113.5

申请日：2001-02-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Confalonieri, Emanuele ,  Corradi, Andrea ,  Fiorina, Sara

IPC: H03K19/003 ,  H03K19/094

CPC classification number: H03K19/00384

Abstract: Output buffer in which the switching speed of the transistors (4,5) of the output stage (1) is kept constant, independently of the variations of the supply voltage (Vcc) and of the temperature, within the acceptable operating range for the device, by controlling, as a function of the supply voltage and the operating temperature detected by a correction circuit (14), the conductivity of additional transistors (13,15) in series with the transistors (7,8) of the predriving stage (2) which drive the transistors of the output stage in conduction, the transistors being driven by an analog signal (CNTRN, CNTRP) which is generated by the correction circuit (14) and is variable with the supply voltage and the operating temperature.

Abstract translation: 输出缓冲器，其中所述输出级（1）的晶体管（4,5）的开关速度保持恒定，电源电压（Vcc）的变化的unabhängig和温度的，在可接受的工作范围为在该装置内 通过控制，作为电源电压的函数，并且通过校正电路（14）检测到的工作温度，附加晶体管（13,15）串联在预驱动级的晶体管（7,8）的电导率（2 ）你推动传导所述输出级的晶体管，该晶体管由在由所述校正电路（14）产生的，并与电源电压和工作温度变量的模拟信号（CNTRN，CNTRP）所有驱动。