公开(公告)号：EP1643558B1

公开(公告)日：2012-05-02

申请号：EP04425733.5

申请日：2004-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferrucio ,  Ferla, Giuseppe ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/732 ,  H01L29/861 ,  H01L29/417 ,  H01L29/06 ,  H01L21/336 ,  H01L21/331 ,  H01L21/329 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

公开(公告)号：EP1432037A3

公开(公告)日：2005-06-22

申请号：EP03079092.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferrucio

IPC: H01L27/06

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate (1, 2; 1, 20) of a first conductivity type is shown. The device comprises a plurality of body region stripes (3) of a second conductivity type which are adjacent and parallel to each other, a first metal layer (12) placed over said substrate (1, 2; 1, 20) and a second metal layer placed under said substrate (1, 2; 1, 20). The device comprises a plurality of elementary structures (6, 7) parallel to each other each one of which comprises first zones provided with a silicon oxide layer (6) placed over a portion of the substrate which is comprised between two adjacent body region stripes (3), a polysilicon layer (7) superimposed to the silicon oxide layer (6), a dielectric layer (11) placed over and around the polysilicon layer (7). Some body region stripes (3) comprise source regions (10) of the first conductivity type which are placed adjacent to the first zones of the elementary structures (6, 7) to form elementary cells of said MOS transistor. The elementary structures (6, 7) and the body regions stripes (3) extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer (12) contacts the source regions (10). At least one elementary structure (6, 7) comprises at least a second zone (8) adapted to allow the direct contact between the first metal layer (12) and the underlying substrate portion (5) arranged between two adiacent body regions stripes (3) to perform the Schottky diode.

公开(公告)号：EP1432037A2

公开(公告)日：2004-06-23

申请号：EP03079092.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferrucio

IPC: H01L27/06

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate (1, 2; 1, 20) of a first conductivity type is shown. The device comprises a plurality of body region stripes (3) of a second conductivity type which are adjacent and parallel to each other, a first metal layer (12) placed over said substrate (1, 2; 1, 20) and a second metal layer placed under said substrate (1, 2; 1, 20). The device comprises a plurality of elementary structures (6, 7) parallel to each other each one of which comprises first zones provided with a silicon oxide layer (6) placed over a portion of the substrate which is comprised between two adjacent body region stripes (3), a polysilicon layer (7) superimposed to the silicon oxide layer (6), a dielectric layer (11) placed over and around the polysilicon layer (7). Some body region stripes (3) comprise source regions (10) of the first conductivity type which are placed adjacent to the first zones of the elementary structures (6, 7) to form elementary cells of said MOS transistor. The elementary structures (6, 7) and the body regions stripes (3) extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer (12) contacts the source regions (10). At least one elementary structure (6, 7) comprises at least a second zone (8) adapted to allow the direct contact between the first metal layer (12) and the underlying substrate portion (5) arranged between two adiacent body regions stripes (3) to perform the Schottky diode.

Abstract translation: 示出了包括形成在第一导电类型的半导体衬底（1,2; 1,20）上的MOS晶体管和肖特基二极管的集成器件。 该装置包括彼此相邻并平行的多个第二导电类型的体区条纹（3），放置在所述基片（1,2; 1,20）上的第一金属层（12）和第二金属层 层（1,2; 1,20）。 该装置包括彼此平行的多个基本结构（6,7），每个基本结构包括第一区域，第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层（6） 3），重叠到氧化硅层（6）的多晶硅层（7），放置在多晶硅层（7）上方和周围的电介质层（11）。 一些体区条纹（3）包括与基本结构（6,7）的第一区相邻放置的第一导电类型的源区（10），以形成所述MOS晶体管的元件。 基本结构（6,7）和体区条纹（3）以横向方式纵向延伸，以在MOS晶体管的基本单元中形成通道，并且第一金属层（12）接触源区（10 ）。 至少一个基本结构（6,7）包括至少第二区域（8），其适于允许第一金属层（12）与布置在两个相邻主体区域（3）之间的下面的基底部分（5）之间的直接接触 ）来执行肖特基二极管。

公开(公告)号：EP1432037B1

公开(公告)日：2008-12-03

申请号：EP03079092.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferrucio

IPC: H01L27/06

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

公开(公告)号：EP1643558A1

公开(公告)日：2006-04-05

申请号：EP04425733.5

申请日：2004-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferrucio ,  Ferla, Giuseppe ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

Abstract: A vertical conduction electronic power device and corresponding realisation method, the device being integrated on a semiconductor substrate (10) and comprising respective gate (20), source (25) and drain (30) areas, realised in an epitaxial layer (40) arranged on said semiconductor substrate (10) and comprising respective gate (21), source (26) and drain (31) metallisations realised by means of a first metallisation level as well as gate (60), source and drain (70) terminals or pads realised by means of a second metallisation level. The device is configured as a set of modular areas (100) extending parallel to each other, each having a rectangular elongate source area (25) perimetrically surrounded by a narrow gate area (20), and separated from each other by regions (30a) with drain area (30) extending parallel and connected at the opposite ends thereof to a second closed region (30b) with drain area (30) forming a device outer peripheral edge; as well as a sinker structure (45) extending perpendicularly to the substrate and formed by a grid of sinker (S) located below both the first parallel regions (30a) and the second closed region (30b) with drain area (30) in order to favour a conductive channel for a current coming from the source area (25) and directed towards the drain area (30) across the substrate (10).

Abstract translation: 一种垂直传导电子功率器件及相应的实现方法，该器件集成在半导体衬底（10）上并且包括在外延层（40）中实现的相应的栅极（20），源极（25）和漏极（30） 在所述半导体衬底（10）上并且包括相应的栅极（21），借助于第一金属化级别实现的源极（26）和漏极（31），以及栅极（60），源极和漏极（70）端子或焊盘 通过第二金属化水平实现。 该装置被配置为一组彼此平行延伸的模块化区域（100），每组具有由狭窄的栅极区域（20）围绕周边的矩形细长的源区域（25），并且由区域（30a）彼此分离， 其中漏区30在其相对端平行延伸并连接到具有形成器件外周边缘的漏区（30）的第二闭合区（30b）; 以及垂直于衬底延伸并由位于两个第一平行区域（30a）和第二闭合区域（30b）下方的沉降片（S）的栅格形成的沉降片结构（45），排列区域（30）依次排列有排水区域 有利于来自源极区域（25）的电流的导电通道，并且穿过衬底（10）引导到漏极区域（30）。