公开(公告)号：EP1045434A1

公开(公告)日：2000-10-18

申请号：EP99830216.0

申请日：1999-04-15

Applicant: STMicroelectronics S.r.l.

Inventor： Caruso, Davide ,  Ranieri, Vito ,  Saggio, Mario ,  Stagnitti, Umberto

IPC: H01L21/322 ,  H01L21/265

CPC classification number: H01L21/26506 ,  H01L21/3223 ,  H01L21/3226

Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front (3) and back (4) surfaces of a semiconductor material wafer (2). The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface (4) of the semiconductor wafer (2) prior to starting the manufacturing process for the electronic devices, essentially before the step of cleaning the front surface (3) of the wafer (2).

Abstract translation: 本发明涉及一种用于制造电子器件的方法在由两个相对的前（3）和背面限定的半导体基板单片集成（4）的半导体材料晶片（2）的表面上。 该方法至少包括注入惰性气体的离子的步骤，随后通过定向以形成由所述气体的蒸发在半导体吸除微孔热处理。 离子注入步骤是通过背表面上进行（4）的半导体晶片（2）之前，开始制造过程的电子装置，清洗晶片的前表面（3）的步骤之前，从本质上（2） ，

公开(公告)号：EP1335507B1

公开(公告)日：2005-09-14

申请号：EP02425043.3

申请日：2002-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Coffa, Salvatore ,  Frisina, Ferruccio

IPC: H04B10/00

CPC classification number: H04B10/801

公开(公告)号：EP1335507A1

公开(公告)日：2003-08-13

申请号：EP02425043.3

申请日：2002-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Coffa, Salvatore ,  Frisina, Ferruccio

IPC: H04B10/00

CPC classification number: H04B10/801

Abstract: The invention relates to a method and an isolation device for providing optimum galvanic isolation between two low-voltage electronic devices (A,B), with the devices (A,B) being optically coupled together. The isolation device is essentially an opto-electronic integrated structure comprising a waveguide (17) that is formed between two separate circuit portions integrated in respective regions (13,13') of the same semiconductor substrate.
Thus, the circuit portions (A,B) are fully galvanically isolated from each other, while the optical signal is transmitted therebetween through an integrated waveguide that is photolithographically patterned in the semiconductor.

Abstract translation: 本发明涉及一种方法和设备，用于提供最佳的电流隔离两个低电压电子设备（A，B）之间，与所述设备（A，B）光学耦合在一起的隔离。 隔离装置是本质上对光电集成结构，其包括波导（17）那样被集成在同一半导体衬底的respectivement区域（13,13“）两个独立的电路部分之间形成。 因此，电路部（A，B）是完全流电隔离海誓山盟，而光信号是通过对集成波导之间的反式mitted有眼在半导体光刻图案化。

公开(公告)号：EP1432037A3

公开(公告)日：2005-06-22

申请号：EP03079092.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferrucio

IPC: H01L27/06

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate (1, 2; 1, 20) of a first conductivity type is shown. The device comprises a plurality of body region stripes (3) of a second conductivity type which are adjacent and parallel to each other, a first metal layer (12) placed over said substrate (1, 2; 1, 20) and a second metal layer placed under said substrate (1, 2; 1, 20). The device comprises a plurality of elementary structures (6, 7) parallel to each other each one of which comprises first zones provided with a silicon oxide layer (6) placed over a portion of the substrate which is comprised between two adjacent body region stripes (3), a polysilicon layer (7) superimposed to the silicon oxide layer (6), a dielectric layer (11) placed over and around the polysilicon layer (7). Some body region stripes (3) comprise source regions (10) of the first conductivity type which are placed adjacent to the first zones of the elementary structures (6, 7) to form elementary cells of said MOS transistor. The elementary structures (6, 7) and the body regions stripes (3) extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer (12) contacts the source regions (10). At least one elementary structure (6, 7) comprises at least a second zone (8) adapted to allow the direct contact between the first metal layer (12) and the underlying substrate portion (5) arranged between two adiacent body regions stripes (3) to perform the Schottky diode.

公开(公告)号：EP1432037A2

公开(公告)日：2004-06-23

申请号：EP03079092.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferrucio

IPC: H01L27/06

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate (1, 2; 1, 20) of a first conductivity type is shown. The device comprises a plurality of body region stripes (3) of a second conductivity type which are adjacent and parallel to each other, a first metal layer (12) placed over said substrate (1, 2; 1, 20) and a second metal layer placed under said substrate (1, 2; 1, 20). The device comprises a plurality of elementary structures (6, 7) parallel to each other each one of which comprises first zones provided with a silicon oxide layer (6) placed over a portion of the substrate which is comprised between two adjacent body region stripes (3), a polysilicon layer (7) superimposed to the silicon oxide layer (6), a dielectric layer (11) placed over and around the polysilicon layer (7). Some body region stripes (3) comprise source regions (10) of the first conductivity type which are placed adjacent to the first zones of the elementary structures (6, 7) to form elementary cells of said MOS transistor. The elementary structures (6, 7) and the body regions stripes (3) extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer (12) contacts the source regions (10). At least one elementary structure (6, 7) comprises at least a second zone (8) adapted to allow the direct contact between the first metal layer (12) and the underlying substrate portion (5) arranged between two adiacent body regions stripes (3) to perform the Schottky diode.

Abstract translation: 示出了包括形成在第一导电类型的半导体衬底（1,2; 1,20）上的MOS晶体管和肖特基二极管的集成器件。 该装置包括彼此相邻并平行的多个第二导电类型的体区条纹（3），放置在所述基片（1,2; 1,20）上的第一金属层（12）和第二金属层 层（1,2; 1,20）。 该装置包括彼此平行的多个基本结构（6,7），每个基本结构包括第一区域，第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层（6） 3），重叠到氧化硅层（6）的多晶硅层（7），放置在多晶硅层（7）上方和周围的电介质层（11）。 一些体区条纹（3）包括与基本结构（6,7）的第一区相邻放置的第一导电类型的源区（10），以形成所述MOS晶体管的元件。 基本结构（6,7）和体区条纹（3）以横向方式纵向延伸，以在MOS晶体管的基本单元中形成通道，并且第一金属层（12）接触源区（10 ）。 至少一个基本结构（6,7）包括至少第二区域（8），其适于允许第一金属层（12）与布置在两个相邻主体区域（3）之间的下面的基底部分（5）之间的直接接触 ）来执行肖特基二极管。

公开(公告)号：EP1160873A1

公开(公告)日：2001-12-05

申请号：EP00830360.4

申请日：2000-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferruccio ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634

Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and apart (1) of said power device which is placed between zones where the elementary active units are formed. The part (1) of the power device comprises at least two heavily doped body regions (4) of a first conductivity type which are formed in a semiconductor layer (3) of a second conductivity type, a first lightly doped semiconductor region (5) of the first conductivity type which is placed laterally between the two body regions (4). The first semiconductor region (5) is placed under a succession of a thick silicon oxide layer (9), a polysilicon layer (10) and a metal layer (13). A plurality of second lightly doped semiconductor regions (6) of the first conductivity type are placed under said at least two heavily doped body regions (4) and under said first lightly doped semiconductor region (5) of the first conductivity type, each region (6) of said plurality of second lightly doped semiconductor regions (6) of the first conductivity type being separated from the other by portions of said semiconductor layer (3) of the second conductivity type.

Abstract translation: 描述了一种MOS技术功率器件，其包括多个基本有源单元，并且分离（1）所述功率器件，放置在形成基本有源单元的区域之间。 功率器件的部分（1）包括形成在第二导电类型的半导体层（3）中的至少两个第一导电类型的重掺杂体区域（4），第一轻掺杂半导体区域（5） 的横向放置在两个主体区域（4）之间的第一导电类型。 第一半导体区域（5）被放置在厚氧化硅层（9），多晶硅层（10）和金属层（13）的一连串之下。 第一导电类型的多个第二轻掺杂半导体区域（6）放置在所述至少两个重掺杂体区域（4）的下方，并且位于第一导电类型的所述第一轻掺杂半导体区域（5）的下方，每个区域 所述第一导电类型的所述多个第二轻掺杂半导体区域（6）的所述第二导电类型的所述半导体层（3）的一部分与所述第二导电类型的所述多个第二轻掺杂半导体区域（6）分离。

公开(公告)号：EP1641029A1

公开(公告)日：2006-03-29

申请号：EP04425715.2

申请日：2004-09-27

Applicant: STMicroelectronics S.r.l.

Inventor： Roccaforte, Fabrizio ,  Raineri, Vito ,  La Via, Francesco ,  Saggio, Mario

IPC: H01L21/04

CPC classification number: H01L21/0435 ,  H01L21/0415

Abstract: Process for the realisation of a Schottky contact on an epitaxial layer of a semiconductor substrate (1), of the type comprising a deposition step (16) of a conductive metallic layer (18) on a surface of the epitaxial layer (32), with achievement of a interface region (20) of conductive metallic layer /semiconductor. The process further comprises a ionic irradiation step (22) directed towards the surface of the epitaxial layer (32) for forming a modified intermediate layer (26, 126) of at least one surface portion (15) of the epitaxial layer (32) for making the electric behaviour of the interface region (20) substantially dependant on the contact between the conductive metallic layer and the obtained modified intermediate layer (26, 126).

Abstract translation: 在半导体衬底（1）的外延层上实现肖特基接触的方法，其包括在外延层（32）的表面上的导电金属层（18）的沉积步骤（16）的类型，其中， 实现导电金属层/半导体的界面区域（20）。 该方法还包括指向外延层（32）的表面的离子照射步骤（22），用于形成外延层（32）的至少一个表面部分（15）的改性中间层（26,126），用于 使得界面区域（20）的电气行为基本上取决于导电金属层与所获得的改性中间层（26,126）之间的接触。

公开(公告)号：EP1225639A1

公开(公告)日：2002-07-24

申请号：EP01830031.9

申请日：2001-01-22

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Lanois, Frederic ,  Frisina, Ferruccio

IPC: H01L29/872

CPC classification number: H01L29/0634 ,  H01L29/872

Abstract: The present invention relates to a Schottky barrier diode comprising a substrate region (9) of a first conductivity type formed in a semiconductor material layer (10) of same conductivity type and a metal layer (12), characterized in that at least a doped region (13) of a second conductive type is formed in said semiconductor layer (10), each one of said doped regions (13) being disposed under said material layer (10) and being separated from other doped regions (13) by portions of said semiconductor layer (10).

Abstract translation: 本发明涉及一种肖特基势垒二极管，其包括形成在具有相同导电类型的半导体材料层（10）中的第一导电类型的衬底区域（9）和金属层（12），其特征在于，至少掺杂区域 在所述半导体层（10）中形成第二导电类型（13），每个所述掺杂区域（13）设置在所述材料层（10）的下方，并且与所述第二导电类型的部分与其它掺杂区域（13）分离， 半导体层（10）。

公开(公告)号：EP0993053A1

公开(公告)日：2000-04-12

申请号：EP98830592.6

申请日：1998-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： Polman, Albert ,  Hamelin, Nicholas ,  Kik, Peter ,  Coffa, Salvatore ,  Frisina, Ferruccio ,  Saggio, Mario

IPC: H01L31/108 ,  H01L31/0288 ,  G02B6/42

CPC classification number: G02B6/12004 ,  H01L31/0352 ,  H01L31/103

Abstract: The infrared detector device (1) comprises a PN junction (9, 10) formed by a first semiconductor material region (9) doped with rare earth ions and by a second semiconductor material region (10) of opposite doping type (P). The detector device comprises a waveguide (8) formed by a projecting structure (6) extending on a substrate (2) including a reflecting layer (4) and laterally delimited by a protection and containment oxide region (11). At least one portion of the waveguide (8) is formed by the PN junction and has an end fed with light to be detected. The detector device (1) has electrodes (18, 13) disposed laterally to and on the waveguide (8) to allow an efficient gathering of charge carriers generated by photoconversion.

Abstract translation: 红外线检测器装置（1）包括由第一半导体材料区域而形成的PN结（9，10）（9）掺杂有稀土离子和由相反的掺杂类型（P）的第二半导体材料区（10）。 该检测器装置包括一个波导（8）由形成突出结构（6）延伸的基板上（2）包括反射层（4）和晚期反弹由保护和容纳氧化物区（11）分隔。 在波导的至少一个部分（8）是由PN结形成并且具有端馈送有被检测光。 所述检测器装置（1）具有电极（18，13），其设置尾盘反弹并在波导（8），以允许在由光转换产生的载流子收集效率。

公开(公告)号：EP1432037B1

公开(公告)日：2008-12-03

申请号：EP03079092.7

申请日：2003-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferrucio

IPC: H01L27/06

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806