公开(公告)号：EP2320296A1

公开(公告)日：2011-05-11

申请号：EP10189494.7

申请日：2010-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Giaquinta, Maria ,  Grasso, Rosario Roberto

IPC: G05F3/30 ,  H03F3/347

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

Abstract: A bandgap voltage reference circuit ( 100' ) for generating a bandgap reference voltage ( Vbg ) according to a first current ( Iptat ) is provided. Said circuit comprises a current generator ( 104 ) controlled by a first driving voltage ( Vpgate ) to generate the first current ( Iptat ) depending on the driving voltage. Said circuit further comprises a first reference circuit clement (102 ) adapted to generate a first reference voltage ( Vpluse ) based on the first current and a second reference circuit element ( 106 ) adapted to generate a second reference voltage ( Vminuse ) according to the first current. The circuit further comprises an operational amplifier ( 124' ) having a first input terminal coupled with the first circuit element for receiving a first reference input voltage ( Vplus ) based on the first reference voltage, a second input terminal coupled with the second reference circuit element for receiving a second input voltage ( Vminus ) based on the second reference voltage, and an output terminal coupled with the current generator to provide the first driving voltage. The circuit also comprises a control circuit ( 134 ). Said control circuit comprises first capacitive means ( 136 ) having a first terminal coupled with the first reference circuit element to receive the first reference voltage and a second terminal coupled with the first input terminal to provide the first input voltage. The control circuit further comprises second capacitive means ( 138 ) comprising a first terminal coupled with the second reference circuit element for receiving the second reference voltage and a second terminal coupled with the second input terminal to provide the second input voltage. The control circuit further comprises first biasing means ( 140' ) for selectively providing a first common-mode voltage ( Vcm ) to the second terminal of the first and second capacitive means. The operational amplifier is an offset compensated operational amplifier further comprising a first compensation terminal for receiving the first common-mode voltage and a second compensation terminal coupled with a compensation offset management circuit ( 600 ) for receiving a first compensation voltage ( Vc1 ). The offset management circuit comprises an auxiliary operational amplifier ( 902 ) having a first input terminal adapted to receive a third input voltage ( Vplus2 ) corresponding to the first input voltage, a second input terminal adapted to receive a fourth input voltage ( Vminus2 ) corresponding to the second input voltage and an output terminal adapted to be selectively coupled with a second compensation terminal of the operational amplifier for providing the first compensation voltage.

Abstract translation: 提供了用于根据第一电流（Iptat）产生带隙参考电压（Vbg）的带隙电压参考电路（100'）。 所述电路包括由第一驱动电压（Vpgate）控制的电流发生器（104），以根据驱动电压产生第一电流（Iptat）。 所述电路还包括适于基于第一电流产生第一参考电压（Vpluse）的第一参考电路元件（102）和适于根据第一电流产生第二参考电压（Vminuse）的第二参考电路元件（106） 当前。 电路还包括运算放大器（124'），其具有与第一电路元件耦合的第一输入端，用于基于第一参考电压接收第一参考输入电压（Vplus）;第二输入端与第二参考电路元件 用于接收基于第二参考电压的第二输入电压（Vminus）以及与电流发生器耦合的输出端以提供第一驱动电压。 电路还包括控制电路（134）。 所述控制电路包括具有与第一参考电路元件耦合以接收第一参考电压的第一端子的第一电容装置（136）和与第一输入端耦合以提供第一输入电压的第二端子。 控制电路还包括第二电容装置（138），包括与第二参考电路元件耦合以接收第二参考电压的第一端子和与第二输入端子耦合以提供第二输入电压的第二端子。 控制电路还包括用于选择性地向第一和第二电容装置的第二端提供第一共模电压（Vcm）的第一偏置装置（140'）。 所述运算放大器是还包括用于接收所述第一共模电压的第一补偿端子和与用于接收第一补偿电压（Vc1））的补偿偏移管理电路（600）耦合的第二补偿端的偏移补偿运算放大器。 偏移管理电路包括辅助运算放大器（902），其具有适于接收对应于第一输入电压的第三输入电压（Vplus2）的第一输入端子，适于接收与第一输入端相对应的第四输入电压（Vminus2）的第二输入端子 所述第二输入电压和输出端子适于与所述运算放大器的第二补偿端子选择性耦合，以提供所述第一补偿电压。

公开(公告)号：EP2924878B1

公开(公告)日：2019-01-30

申请号：EP15161796.6

申请日：2015-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Giaquinta, Maria

IPC: H03F3/45 ,  H03F1/08 ,  H03F1/14 ,  G11C29/02 ,  G11C16/12 ,  H03K3/012 ,  H03K3/353

公开(公告)号：EP2320295A1

公开(公告)日：2011-05-11

申请号：EP10189487.1

申请日：2010-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Grasso, Rosario Roberto ,  Giaquinta, Maria

IPC: G05F3/30 ,  H03F3/393

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

Abstract: A bandgap voltage reference circuit ( 100 ) for generating a bandgap voltage reference ( Vbg ). Said circuit comprises a current generator ( 104 ) controlled by a first driving voltage ( Vpgate ) for generating a first current ( Iptat ) depending on the driving voltage, and a first reference circuit element ( 102 ) coupled to the controlled current generator ( 104 ) for receiving the first current and generating a first reference voltage ( Vpluse ) in response to the first current. The circuit further comprises a second reference circuit element ( 106 ) for receiving a second current ( Iptat ) corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage ( Vminuse ) in response to the second current. Said circuit further comprises a third reference circuit element ( 128 ) for receiving a third current ( Iptat ) corresponding to the first current and generating the bandgap reference voltage in response to the third current, and an operational amplifier ( 124 ). The operational amplifier has a first input terminal coupled to the first circuit element for receiving a first reference voltage input ( Vplus ) based on the first reference voltage, a second input terminal coupled to the second reference circuit element for receive a second input voltage ( Vminus ) based on the second reference voltage and an output terminal coupled to the controlled current generator to provide the first driving voltage ( Vpgate ) to the current generator according to the difference between the first input voltage and the second input voltage. The circuit also comprises a control circuit ( 134 ) comprising first capacitive means ( 136 ) and second capacitive means ( 138 ). The first capacitive means have a first terminal coupled to the first reference circuit element to receive the first reference voltage and a second terminal coupled to the first input terminal to provide the first input voltage. The second capacitive means comprise a first terminal coupled to the second reference circuit element for receiving the second reference voltage and a second terminal coupled to the second input terminal to provide the second input voltage. The control circuit also comprises biasing means ( 140 ) to selectively provide a common-mode voltage ( Vcm ) to the second terminals of the first and second capacitive means.

Abstract translation: 一种用于产生带隙电压基准（Vbg）的带隙电压参考电路（100）。 所述电路包括由第一驱动电压（Vpgate）控制的电流发生器（104），用于根据驱动电压产生第一电流（Iptat），以及耦合到受控电流发生器（104）的第一参考电路元件（102） 用于接收第一电流并响应于第一电流产生第一参考电压（Vpluse）。 电路还包括用于接收对应于第一电流的第二电流（Iptat）的第二参考电路元件（106） 所述第二参考电路元件适于响应于第二电流产生第二参考电压（Vminuse）。 所述电路还包括第三参考电路元件（128），用于接收对应于第一电流的第三电流（Iptat）并响应于第三电流产生带隙参考电压，以及运算放大器（124）。 运算放大器具有耦合到第一电路元件的第一输入端，用于基于第一参考电压接收第一参考电压输入（Vplus）;耦合到第二参考电路元件的第二输入端，用于接收第二输入电压（Vminus ）和耦合到受控电流发生器的输出端子，以根据第一输入电压和第二输入电压之间的差异向电流发生器提供第一驱动电压（Vpgate）。 电路还包括包括第一电容装置（136）和第二电容装置（138）的控制电路（134）。 第一电容装置具有耦合到第一参考电路元件以接收第一参考电压的第一端子和耦合到第一输入端子以提供第一输入电压的第二端子。 第二电容装置包括耦合到第二参考电路元件用于接收第二参考电压的第一端子和耦合到第二输入端子以提供第二输入电压的第二端子。 控制电路还包括偏置装置（140），以选择性地向第一和第二电容装置的第二端子提供共模电压（Vcm）。

公开(公告)号：EP2924878A1

公开(公告)日：2015-09-30

申请号：EP15161796.6

申请日：2015-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Giaquinta, Maria

IPC: H03F3/45 ,  H03F1/08 ,  H03F1/14 ,  G11C16/12

CPC classification number: G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  H03F1/0205 ,  H03F1/086 ,  H03F1/14 ,  H03F3/16 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/129 ,  H03F2200/153 ,  H03F2200/45 ,  H03F2200/516 ,  H03F2203/45138 ,  H03F2203/45364 ,  H03F2203/45511 ,  H03F2203/45512 ,  H03K3/012 ,  H03K3/353

Abstract: A solution for amplifying an input signal (Vin) into an output signal (Vo) to be applied to an electric load comprising at least one capacitive component (Cl) is proposed. A corresponding amplifier stage comprises a pre-amplifier module (305) adapted to receive a first supply voltage and an output module (310) adapted to receive a second supply voltage. The pre-amplifier module comprises: a first gain block (315) adapted to pre-amplify the input signal into a first pre-amplified signal, a second gain block (320) adapted to pre-amplify the input signal into a second preamplified signal, a feedback block (325) adapted to feed-back the output signal into a feedback signal, and a combination element (330) adapted to combine the first pre-amplified signal and the feedback signal into a combined signal, and wherein the output module is adapted to combine the combined signal and the second pre-amplified signal into the output signal.

Abstract translation: 提出了一种用于将输入信号（Vin）放大为要施加到包括至少一个电容分量（C1）的电负载的输出信号（Vo）的解决方案。 相应的放大器级包括适于接收第一电源电压的前置放大器模块（305）和适于接收第二电源电压的输出模块（310）。 前置放大器模块包括：适于将输入信号预放大成第一预放大信号的第一增益块（315），适于将输入信号预放大成第二预放大信号的第二增益块（320） ，适于将所述输出信号反馈到反馈信号中的反馈块（325）以及适于将所述第一预放大信号和所述反馈信号组合成组合信号的组合元件（330），并且其中所述输出模块 适于将组合信号和第二预放大信号组合成输出信号。

公开(公告)号：EP2919386A1

公开(公告)日：2015-09-16

申请号：EP15159122.9

申请日：2015-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Giaquinta, Maria

IPC: H03F3/45 ,  H03F1/34 ,  H03F3/347

CPC classification number: G11C16/06 ,  H03F1/34 ,  H03F3/347 ,  H03F3/45 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2200/156 ,  H03F2200/375 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/45332 ,  H03F2203/45514 ,  H03F2203/45546 ,  H03F2203/45632 ,  H03M1/661

Abstract: A digital-to-analog converter (115) is proposed. The digital-to-analog converter (115) comprises a conversion block (205) for receiving a digital value ( D D ) and providing a corresponding first analog value ( D A ), and an amplification block (210) for receiving said first analog value ( D A ) and providing a second analog value ( V P ) amplified by an amplification factor (G) with respect to said first analog value ( D A ). Said amplification block (210) comprises a first input terminal for receiving said first analog value ( D A ), a second input terminal, and an output terminal for providing said second analog value ( V P ). Said amplification block (210) further comprises a first capacitive element (C A ) having a first (T A1 ) and a second (T A2 ) terminals connected to the output terminal and the second input terminal, respectively, of the amplification block (210), and a second capacitive element (C B ) having a first (T B1 ) and a second (T B2 ) terminals connected to the second terminal (T A2 ) of the first capacitive element (C A ) and to a reference terminal, respectively, said first (C A ) and second (C B ) capacitive elements determining said amplification factor ( G ). Said amplification block (210) further comprises a circuit stage (C AR ,C BR ,S W1 -S W4 , 120 , ϕ 1 -ϕ 3 ) for recovering, at each predefined time period ( T R ) , an operative charge at the first terminal ( T B1 ) of said second capacitive element (C B ), and hence the second analog value ( V P ) to the output terminal of said amplification block (210).

Abstract translation: 提出了一种数模转换器（115）。 数模转换器（115）包括用于接收数字值（DD）并提供对应的第一模拟值（DA）的转换块（205），以及用于接收所述第一模拟值的放大块（210） DA），并提供相对于所述第一模拟值（DA）由放大因子（G）放大的第二模拟值（VP）。 所述放大块（210）包括用于接收所述第一模拟值（D A）的第一输入端，第二输入端和用于提供所述第二模拟值（V P）的输出端。 所述放大块（210）还包括具有分别连接到放大块（210）的输出端和第二输入端的第一（T A1）和第二（T A2）端的第一电容元件（CA） 和具有分别连接到第一电容元件（CA）的第二端子（T A2）和参考端子的第一（T B1）和第二（T B2）端子的第二电容元件（CB），所述第二电容元件 第一（CA）和第二（CB）电容元件确定所述放大因子（G）。 所述放大块（210）还包括一个电路级（C AR，C BR，S W1 -S W4,120，...），用于在每个预定时间段（TR）恢复第一 所述第二电容元件（CB）的端子（T B1），并且因此到所述放大块（210）的输出端的第二模拟值（VP）。