公开(公告)号：EP2320296A1

公开(公告)日：2011-05-11

申请号：EP10189494.7

申请日：2010-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Giaquinta, Maria ,  Grasso, Rosario Roberto

IPC: G05F3/30 ,  H03F3/347

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

Abstract: A bandgap voltage reference circuit ( 100' ) for generating a bandgap reference voltage ( Vbg ) according to a first current ( Iptat ) is provided. Said circuit comprises a current generator ( 104 ) controlled by a first driving voltage ( Vpgate ) to generate the first current ( Iptat ) depending on the driving voltage. Said circuit further comprises a first reference circuit clement (102 ) adapted to generate a first reference voltage ( Vpluse ) based on the first current and a second reference circuit element ( 106 ) adapted to generate a second reference voltage ( Vminuse ) according to the first current. The circuit further comprises an operational amplifier ( 124' ) having a first input terminal coupled with the first circuit element for receiving a first reference input voltage ( Vplus ) based on the first reference voltage, a second input terminal coupled with the second reference circuit element for receiving a second input voltage ( Vminus ) based on the second reference voltage, and an output terminal coupled with the current generator to provide the first driving voltage. The circuit also comprises a control circuit ( 134 ). Said control circuit comprises first capacitive means ( 136 ) having a first terminal coupled with the first reference circuit element to receive the first reference voltage and a second terminal coupled with the first input terminal to provide the first input voltage. The control circuit further comprises second capacitive means ( 138 ) comprising a first terminal coupled with the second reference circuit element for receiving the second reference voltage and a second terminal coupled with the second input terminal to provide the second input voltage. The control circuit further comprises first biasing means ( 140' ) for selectively providing a first common-mode voltage ( Vcm ) to the second terminal of the first and second capacitive means. The operational amplifier is an offset compensated operational amplifier further comprising a first compensation terminal for receiving the first common-mode voltage and a second compensation terminal coupled with a compensation offset management circuit ( 600 ) for receiving a first compensation voltage ( Vc1 ). The offset management circuit comprises an auxiliary operational amplifier ( 902 ) having a first input terminal adapted to receive a third input voltage ( Vplus2 ) corresponding to the first input voltage, a second input terminal adapted to receive a fourth input voltage ( Vminus2 ) corresponding to the second input voltage and an output terminal adapted to be selectively coupled with a second compensation terminal of the operational amplifier for providing the first compensation voltage.

Abstract translation: 提供了用于根据第一电流（Iptat）产生带隙参考电压（Vbg）的带隙电压参考电路（100'）。 所述电路包括由第一驱动电压（Vpgate）控制的电流发生器（104），以根据驱动电压产生第一电流（Iptat）。 所述电路还包括适于基于第一电流产生第一参考电压（Vpluse）的第一参考电路元件（102）和适于根据第一电流产生第二参考电压（Vminuse）的第二参考电路元件（106） 当前。 电路还包括运算放大器（124'），其具有与第一电路元件耦合的第一输入端，用于基于第一参考电压接收第一参考输入电压（Vplus）;第二输入端与第二参考电路元件 用于接收基于第二参考电压的第二输入电压（Vminus）以及与电流发生器耦合的输出端以提供第一驱动电压。 电路还包括控制电路（134）。 所述控制电路包括具有与第一参考电路元件耦合以接收第一参考电压的第一端子的第一电容装置（136）和与第一输入端耦合以提供第一输入电压的第二端子。 控制电路还包括第二电容装置（138），包括与第二参考电路元件耦合以接收第二参考电压的第一端子和与第二输入端子耦合以提供第二输入电压的第二端子。 控制电路还包括用于选择性地向第一和第二电容装置的第二端提供第一共模电压（Vcm）的第一偏置装置（140'）。 所述运算放大器是还包括用于接收所述第一共模电压的第一补偿端子和与用于接收第一补偿电压（Vc1））的补偿偏移管理电路（600）耦合的第二补偿端的偏移补偿运算放大器。 偏移管理电路包括辅助运算放大器（902），其具有适于接收对应于第一输入电压的第三输入电压（Vplus2）的第一输入端子，适于接收与第一输入端相对应的第四输入电压（Vminus2）的第二输入端子 所述第二输入电压和输出端子适于与所述运算放大器的第二补偿端子选择性耦合，以提供所述第一补偿电压。

公开(公告)号：EP1727153B1

公开(公告)日：2008-10-15

申请号：EP05104465.9

申请日：2005-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Sberno, Giampiero ,  Micciche', Mario ,  Castaldo, Enrico

IPC: G11C16/16

CPC classification number: G11C16/16

公开(公告)号：EP2947660B1

公开(公告)日：2017-04-12

申请号：EP15167701.0

申请日：2015-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Pagano, Santi Nunzio Antonino

IPC: G11C7/12 ,  G11C16/24 ,  G11C16/28

CPC classification number: G11C7/062 ,  G11C7/1051 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002

Abstract: A solution relating to a sense structure is proposed. Particularly, the sense structure (200) comprises a plurality of sense amplifiers (205 i ), each sense amplifier comprising at least one measuring terminal (INm) and a reference terminal (INr) for receiving a measuring current (Im) and a reference current (Ir), respectively, output means (225) for providing an output voltage (Vout) according to a comparison between the measuring current and the reference current, and voltage regulating means in cascode configuration (220m,220r) for regulating a voltage at the measuring terminal and at the reference terminal, the regulating means comprising a measuring regulating transistor (220m) and a reference regulating transistor (220r) having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output means and a control terminal coupled with a biasing terminal (Tb), the sense structure further comprising biasing means (230) for providing a biasing voltage (Vb) to the biasing terminal of all the sense amplifiers, and common regulating means (235) for regulating the biasing voltage for all the sense amplifiers, wherein each sense amplifier further comprises local regulating means (240) for regulating the biasing voltage applied to the biasing terminal, and in that the sense structure further comprises switching means (245) selectively controllable for coupling the local regulating means of each sense amplifier with the common regulating means to refresh the local regulating means in a rest condition and for decoupling the local regulating means of each sense amplifier from the common regulating means in an operative condition.

公开(公告)号：EP2320295A1

公开(公告)日：2011-05-11

申请号：EP10189487.1

申请日：2010-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Grasso, Rosario Roberto ,  Giaquinta, Maria

IPC: G05F3/30 ,  H03F3/393

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

Abstract: A bandgap voltage reference circuit ( 100 ) for generating a bandgap voltage reference ( Vbg ). Said circuit comprises a current generator ( 104 ) controlled by a first driving voltage ( Vpgate ) for generating a first current ( Iptat ) depending on the driving voltage, and a first reference circuit element ( 102 ) coupled to the controlled current generator ( 104 ) for receiving the first current and generating a first reference voltage ( Vpluse ) in response to the first current. The circuit further comprises a second reference circuit element ( 106 ) for receiving a second current ( Iptat ) corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage ( Vminuse ) in response to the second current. Said circuit further comprises a third reference circuit element ( 128 ) for receiving a third current ( Iptat ) corresponding to the first current and generating the bandgap reference voltage in response to the third current, and an operational amplifier ( 124 ). The operational amplifier has a first input terminal coupled to the first circuit element for receiving a first reference voltage input ( Vplus ) based on the first reference voltage, a second input terminal coupled to the second reference circuit element for receive a second input voltage ( Vminus ) based on the second reference voltage and an output terminal coupled to the controlled current generator to provide the first driving voltage ( Vpgate ) to the current generator according to the difference between the first input voltage and the second input voltage. The circuit also comprises a control circuit ( 134 ) comprising first capacitive means ( 136 ) and second capacitive means ( 138 ). The first capacitive means have a first terminal coupled to the first reference circuit element to receive the first reference voltage and a second terminal coupled to the first input terminal to provide the first input voltage. The second capacitive means comprise a first terminal coupled to the second reference circuit element for receiving the second reference voltage and a second terminal coupled to the second input terminal to provide the second input voltage. The control circuit also comprises biasing means ( 140 ) to selectively provide a common-mode voltage ( Vcm ) to the second terminals of the first and second capacitive means.

Abstract translation: 一种用于产生带隙电压基准（Vbg）的带隙电压参考电路（100）。 所述电路包括由第一驱动电压（Vpgate）控制的电流发生器（104），用于根据驱动电压产生第一电流（Iptat），以及耦合到受控电流发生器（104）的第一参考电路元件（102） 用于接收第一电流并响应于第一电流产生第一参考电压（Vpluse）。 电路还包括用于接收对应于第一电流的第二电流（Iptat）的第二参考电路元件（106） 所述第二参考电路元件适于响应于第二电流产生第二参考电压（Vminuse）。 所述电路还包括第三参考电路元件（128），用于接收对应于第一电流的第三电流（Iptat）并响应于第三电流产生带隙参考电压，以及运算放大器（124）。 运算放大器具有耦合到第一电路元件的第一输入端，用于基于第一参考电压接收第一参考电压输入（Vplus）;耦合到第二参考电路元件的第二输入端，用于接收第二输入电压（Vminus ）和耦合到受控电流发生器的输出端子，以根据第一输入电压和第二输入电压之间的差异向电流发生器提供第一驱动电压（Vpgate）。 电路还包括包括第一电容装置（136）和第二电容装置（138）的控制电路（134）。 第一电容装置具有耦合到第一参考电路元件以接收第一参考电压的第一端子和耦合到第一输入端子以提供第一输入电压的第二端子。 第二电容装置包括耦合到第二参考电路元件用于接收第二参考电压的第一端子和耦合到第二输入端子以提供第二输入电压的第二端子。 控制电路还包括偏置装置（140），以选择性地向第一和第二电容装置的第二端子提供共模电压（Vcm）。

公开(公告)号：EP2947660A1

公开(公告)日：2015-11-25

申请号：EP15167701.0

申请日：2015-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Pagano, Santi Nunzio Antonino

IPC: G11C7/12 ,  G11C16/24 ,  G11C16/28

CPC classification number: G11C7/062 ,  G11C7/1051 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002

Abstract: A solution relating to a sense structure is proposed. Particularly, the sense structure (200) comprises a plurality of sense amplifiers (205 i ), each sense amplifier comprising at least one measuring terminal (INm) and a reference terminal (INr) for receiving a measuring current (Im) and a reference current (Ir), respectively, output means (225) for providing an output voltage (Vout) according to a comparison between the measuring current and the reference current, and voltage regulating means in cascode configuration (220m,220r) for regulating a voltage at the measuring terminal and at the reference terminal, the regulating means comprising a measuring regulating transistor (220m) and a reference regulating transistor (220r) having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output means and a control terminal coupled with a biasing terminal (Tb), the sense structure further comprising biasing means (230) for providing a biasing voltage (Vb) to the biasing terminal of all the sense amplifiers, and common regulating means (235) for regulating the biasing voltage for all the sense amplifiers, wherein each sense amplifier further comprises local regulating means (240) for regulating the biasing voltage applied to the biasing terminal, and in that the sense structure further comprises switching means (245) selectively controllable for coupling the local regulating means of each sense amplifier with the common regulating means to refresh the local regulating means in a rest condition and for decoupling the local regulating means of each sense amplifier from the common regulating means in an operative condition.

Abstract translation: 的溶液与感结构的提议。 特别地，感测结构（200）包括读出放大器（205 i）中，每个读出放大器，其包括至少一个测量终端（INM）和用于接收测量电流（Im）和参考电流的参考端子（INR）的多元 （IR），分别输出装置（225），用于雅丁用于在调节电压的提供关于输出电压（Vout），以测量电流和参考电流，以及电压调节级联配置（220米，220R）的装置之间的比较 测量端子和基准端子，所述调节装置包括一个测量调节晶体管（220米）和参考调节晶体管（220R），其具有耦合与测量端子，并与所述基准端子连接的第一导通端子，分别，第二传导端耦接 与输出装置和耦合的偏置端子（Tb）的控制端子，感测结构，还包括用于提供偏压的偏压装置（230） 用于调节的偏置电压对于所有的读出放大器，worin每个读出放大器进一步荷兰国际集团电压（Vb）中的所有读出放大器的偏置端子，以及共同调节装置（235）包括用于调节所述偏置电压本地调节装置（240） 施加到偏置端子，并且在没有感测结构还包括开关装置（245）选择性地控制用于每个读出放大器的局部调节装置与共同调节耦合装置来刷新本地调节在静止状态装置和用于去耦的 从共用调节每个读出放大器的局部调节装置的装置在运行条件。

公开(公告)号：EP1727153A1

公开(公告)日：2006-11-29

申请号：EP05104465.9

申请日：2005-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Sberno, Giampiero ,  Micciche', Mario ,  Castaldo, Enrico

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A non-volatile memory device is proposed. The memory device (100) includes a plurality of blocks (115) of memory cells (125), each block having a common biasing node (SL) for all the memory cells of the block, biasing means (150) for providing a biasing voltage, and selection means (140, 145) for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means (N8, N9, N10) and second switching means (N7) connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means (145) for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.

Abstract translation: 提出了一种非易失性存储器件。 存储器件（100）包括存储器单元（125）的多个块（115），每个块具有用于块的所有存储单元的公共偏置节点（SL），偏置装置（150）用于提供偏置电压 以及用于选择性地将偏置电压施加到所选块的偏置节点的选择装置（140,145），对于每个块，选择装置包括第一开关装置（N8，N9，N10）和第二开关装置（N7） 所述第一开关装置与所述偏置节点连接，所述第二开关装置与所述偏置装置连接，其中所述块的所述第二开关装置并联连接，所述选择装置包括用于闭合所述第一开关装置的装置， 所有块的切换装置和所有块的第二切换装置，并且用于打开每个未选择块的第二切换装置。