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    Differential to single-ended converter
    1.
    发明公开
    Differential to single-ended converter 有权
    Differentialziell nach单极Umsetzer

    公开(公告)号：EP1684418A1

    公开(公告)日：2006-07-26

    申请号：EP05425027.9

    申请日：2005-01-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Copani, Tino ,  Smerzi, Santo Alessandro ,  Girlando, Giovanni ,  Palmisano, Giuseppe

    IPC: H03F3/45

    CPC classification number: H03F3/45174

    Abstract: A converter of a differential input signal into a single-ended output signal, has a differential pair of identical transistors first and second driven by the differential input signal, and a circuit for filtering DC components, connected between the current terminal of the second transistor not in common with the first transistor of the differential pair and an output node of the converter on which the single-ended output signal is generated.
    It generates a single-ended signal without employing a transformer, in lieu thereof the converter includes:

    a current generator biasing the differential pair by means of two output transistors, third and fourth, in current mirror configuration, connected in series with the transistors first and second, respectively;
    degeneration resistors of the transistors of the current mirror, dimensioned such that the gains of the converter for each of the two input nodes of the differential signal are equal and of opposite sign.

    Abstract translation: 将差分输入信号的转换器转换为单端输出信号，具有由差分输入信号驱动的第一和第二相同晶体管的差分对，以及用于滤波直流分量的电路，连接在第二晶体管的电流端子之间， 与差分对的第一晶体管和其上产生单端输出信号的转换器的输出节点相同。 它产生单端信号而不使用变压器，代替其中的转换器包括：电流发生器，通过两个输出晶体管偏置差分对，第三和第四输出晶体管以电流镜配置，首先与晶体管串联连接， 第二，分别; 电流镜的晶体管的退化电阻器的尺寸设计成使得差分信号的两个输入节点中的每一个的转换器的增益相等并且具有相反的符号。

    Low-noise amplifier stage with matching network
    2.
    发明公开
    Low-noise amplifier stage with matching network 有权
    RauscharmeVerstärkerstufemit Anpassungsschaltung

    公开(公告)号：EP1014565A1

    公开(公告)日：2000-06-28

    申请号：EP98830772.4

    申请日：1998-12-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Palmisano, Giuseppe ,  Ferla, Giuseppe ,  Girlando, Giovanni

    IPC: H03F1/56 ,  H03F1/22

    CPC classification number: H03F1/22 ,  H03F1/565 ,  H03F2200/294 ,  H03F2200/372

    Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

    Abstract translation: 放大器级（50）包括在第一（4）和第二（5）参考电位线之间彼此串联连接的第一（2）和第二（3）晶体管。 第一晶体管（2）具有通过第一电感器（12）连接到放大器级（50）的输入端（11）的控制端子（10），连接到第二参考电位线的第一端子（15） （5）通过第二电感器（16）和连接到第二晶体管（3）的第一端子的第三端子（17）。 第二晶体管具有形成放大级（50）的输出的第二端（21），并通过负载电阻（22）连接到第一参考电位线（4）。 为了提高噪声系数，在控制端子（10）和第一晶体管（2）的第一端子（15）之间连接有匹配电容器（51）。

    Prescaling stage for high frequency applications
    4.
    发明公开
    Prescaling stage for high frequency applications 有权
    VorteilerstufefürHochfrequenzanwendungen

    公开(公告)号：EP1603243A1

    公开(公告)日：2005-12-07

    申请号：EP04425401.9

    申请日：2004-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Copani, Tino ,  Smerzi, Santo Alessandro ,  Girlando, Giovanni ,  Palmisano, Giuseppe

    IPC: H03K23/66

    CPC classification number: H03K23/662

    Abstract: A prescaling stage is described of the type comprising at least one bistable circuit in turn including respective master and slave portions (2, 3) inserted between a first and a second voltage reference (Vcc, GND) and feedback connected to each other. Each portion is provided with at least one differential stage (4, 5) supplied by the first voltage reference (Vcc) and connected, by means of a transistor stage (52, 53), to the second voltage reference (GND), as well as a differential pair (6, 7) of cross-coupled transistors, supplied by output terminals of the differential stage (4, 5) and connected, by means of the transistor stage (52, 53), to the second voltage reference (GND). Advantageously according to the invention, each master and slave portion (2, 3) comprises at least one degeneracy capacity (C2, C3) inserted in correspondence with respective terminals of the transistors of the differential pair (6, 7).

    Abstract translation: 描述了包括至少一个双稳态电路的类型的预分压级，其依次包括插入在第一和第二参考电压（Vcc，GND）之间的相应主从部分（2,3）和彼此连接的反馈。 每个部分设置有由第一参考电压（Vcc）提供并通过晶体管级（52,53）连接到第二参考电压（GND）的至少一个差分级（4,5），以及 作为由差分级（4,5）的输出端提供并通过晶体管级（52,53）连接到第二电压基准（GND）的交叉耦合晶体管的差分对（6,7） ）。 有利地，根据本发明，每个主和从部分（2,3）包括与差分对（6,7）的晶体管的各个端子对应地插入的至少一个简并容量（C2，C3）。

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