公开(公告)号：EP2315043A1

公开(公告)日：2011-04-27

申请号：EP10188039.1

申请日：2010-10-19

Applicant: STMicroelectronics S.r.l.

Inventor： Pagani, Alberto

IPC: G01R31/312

CPC classification number: G01R1/06761 ,  G01R1/06711 ,  G01R1/06716 ,  G01R1/06733 ,  G01R1/06766 ,  G01R1/07 ,  G01R1/07314 ,  G01R31/312

Abstract: An aspect of the solution according to an embodiment of the present invention proposes a test apparatus (100, 500) for executing a test of a set of electronic devices (105) having a plurality of electrically conductive terminals (115, 208, 308, 309a, 309b, 408a, 408b). The test apparatus includes a plurality of electrically conductive test probes (135) for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In the solution according to an embodiment of the invention, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for clectro-magnctically coupling the test probe with the terminal.

Abstract translation: 根据本发明的实施例的解决方案的一个方面提出了一种用于执行具有多个导电端子（115,208,308,309a）的一组电子设备（105）的测试的测试设备（100,500） ，309b，408a，408b）。 测试装置包括用于与端子交换电信号的多个导电测试探针（135）和用于将测试探针与电子设备机械耦合的耦合装置。 在根据本发明的实施例的解决方案中，耦合装置包括绝缘装置，用于在执行测试期间将至少部分测试探针中的每一个与至少一个相应的端子电绝缘。 每个测试探头和相应的端子形成电容器，用于将测试探头与终端电磁耦合。

公开(公告)号：EP2290686A3

公开(公告)日：2011-04-20

申请号：EP10174004.1

申请日：2010-08-25

Applicant: STMicroelectronics S.r.l.

Inventor： Pagani, Alberto

IPC: H01L23/58 ,  H01L21/768

CPC classification number: H01L22/14 ,  G01R31/2818 ,  G01R31/2884 ,  H01L22/32 ,  H01L23/481 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A method is described to perform electrical testing and assembly of at least one electronic device (50) comprised in a wafer (100) and comprising at least one pad (51) made in an oxide layer (57) covered by a passivation layer (56), of the type comprising the steps of:
- connecting said at least one electronic device (50) to a testing apparatus;
- providing said electronic device (50) with at least one metallisation layer (54) extending on said passivation layer (56) from said at least one pad (51) to a non active area (55) of said wafer (100). Advantageously according to the invention, the method comprises the steps of:
- performing the electrical testing on wafer of said at least one electronic device (50) placing at least one probe (59) of said testing apparatus on a portion of said at least one extended metallisation layer (54) comprised in said non active area (55);
- performing the cut of said wafer (100), reducing the extension of said at least one metallisation layer (54) extended to the edge of said at least one electronic device (50);
- embedding inside a package said at least one electronic device (50), forming on said at least one metallisation layer (54) extended to the edge means suitable for establishing an electrical connection to at least one circuit means comprised in said package.

公开(公告)号：EP3098584B1

公开(公告)日：2019-09-11

申请号：EP15200285.3

申请日：2015-12-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pagani, Alberto ,  Murari, Bruno ,  Ferrera, Marco ,  Giusti, Domenico ,  Caltabiano, Daniele

IPC: G01L15/00 ,  G01L9/00

公开(公告)号：EP2315364A1

公开(公告)日：2011-04-27

申请号：EP10188100.1

申请日：2010-10-19

Applicant: STMicroelectronics S.r.l.

Inventor： Pagani, Alberto

IPC: H04B5/00

CPC classification number: H01F38/14 ,  H01F2038/146 ,  H02J17/00 ,  H02J50/05 ,  H02J50/10 ,  H02J50/40 ,  H02J50/70 ,  H02J50/80 ,  H04B5/0012 ,  H04B5/0037 ,  H04B5/0075 ,  H04B5/0093

Abstract: An aspect of the solution according to an embodiment of the present invention proposes an electronic system (100a, 100b, 400a, 400b) including a first electronic circuit (105a) and a second electronic circuit (105a'). The electronic system further includes a resonant LC circuit having a resonance frequency for coupling the first electronic circuit and the second electronic circuit; each electronic circuit includes functional means (110a, 110a') for providing a signal at the resonance frequency to be transmitted to the other electronic circuit through the LC circuit and/or for receiving the signal from the other electronic circuit. In the solution according to one or more embodiments of the present invention, the LC circuit includes capacitor means (123a) having at least one first capacitor plate (120a) included in the first electronic circuit and at least one second capacitor plate (120a') included in the second electronic circuit. The LC circuit further includes first inductor means (125a) included in the first electronic circuit and/or second inductor means (425a) included in the second electronic circuit. The at least one capacitor plate (120a, 120a') of each electronic circuit is coupled with the corresponding functional means (110a, 110a') through the possible corresponding inductor means.

Abstract translation: 根据本发明的实施例的解决方案的一个方面提出了一种包括第一电子电路（105a）和第二电子电路（105a'）的电子系统（100a，100b，400a，400b）。 电子系统还包括具有用于耦合第一电子电路和第二电子电路的谐振频率的谐振LC电路; 每个电子电路包括用于通过LC电路提供要发送到另一电子电路的谐振频率的信号和/或用于从另一电子电路接收信号的功能装置（110a，110a'）。 在根据本发明的一个或多个实施例的解决方案中，LC电路包括电容器装置（123a），其具有包括在第一电子电路中的至少一个第一电容器板（120a）和至少一个第二电容器板（120a'）， 包括在第二电子电路中。 LC电路还包括第一电子电路中包括的第一电感器装置（125a）和/或包括在第二电子电路中的第二电感装置（425a）。 每个电子电路的至少一个电容器板（120a，120a'）通过可能的相应的电感器装置与相应的功能装置（110a，110a'）耦合。

公开(公告)号：EP2290686A2

公开(公告)日：2011-03-02

申请号：EP10174004.1

申请日：2010-08-25

Applicant: STMicroelectronics S.r.l.

Inventor： Pagani, Alberto

IPC: H01L23/58 ,  H01L21/768

CPC classification number: H01L22/14 ,  G01R31/2818 ,  G01R31/2884 ,  H01L22/32 ,  H01L23/481 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A method is described to perform electrical testing and assembly of at least one electronic device (50) comprised in a wafer (100) and comprising at least one pad (51) made in an oxide layer (57) covered by a passivation layer (56), of the type comprising the steps of:
- connecting said at least one electronic device (50) to a testing apparatus;
- providing said electronic device (50) with at least one metallisation layer (54) extending on said passivation layer (56) from said at least one pad (51) to a non active area (55) of said wafer (100). Advantageously according to the invention, the method comprises the steps of:
- performing the electrical testing on wafer of said at least one electronic device (50) placing at least one probe (59) of said testing apparatus on a portion of said at least one extended metallisation layer (54) comprised in said non active area (55);
- performing the cut of said wafer (100), reducing the extension of said at least one metallisation layer (54) extended to the edge of said at least one electronic device (50);
- embedding inside a package said at least one electronic device (50), forming on said at least one metallisation layer (54) extended to the edge means suitable for establishing an electrical connection to at least one circuit means comprised in said package.

Abstract translation: 描述了一种执行包括在晶片（100）中的至少一个电子装置（50）的电测试和组装的方法，并且该方法包括在由钝化层（56）覆盖的氧化物层（57）中制成的至少一个垫（51） ），其类型包括以下步骤： - 将所述至少一个电子装置（50）连接到测试装置; - 为所述电子器件（50）提供至少一个在所述钝化层（56）上从所述至少一个焊盘（51）延伸到所述晶片（100）的非有源区（55）的金属化层（54）。 有利地，根据本发明，该方法包括以下步骤： - 在所述至少一个电子装置（50）的晶片上执行电测试，将所述测试装置的至少一个探针（59）放置在所述至少一个 包括在所述非有效区域（55）中的延伸金属化层（54）; - 执行所述晶片（100）的切割，减小延伸到所述至少一个电子器件（50）的边缘的所述至少一个金属化层（54）的延伸; - 在所述封装内嵌入所述至少一个电子器件（50），所述至少一个电子器件在所述至少一个金属化层（54）上形成，所述至少一个金属化层延伸到适于建立到包含在所述封装中的至少一个电路装置的电连接的边缘装置。

公开(公告)号：EP3098584A1

公开(公告)日：2016-11-30

申请号：EP15200285.3

申请日：2015-12-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pagani, Alberto ,  Murari, Bruno ,  Ferrera, Marco ,  Giusti, Domenico ,  Caltabiano, Daniele

IPC: G01L15/00 ,  G01L9/00

CPC classification number: G01L9/0052 ,  G01L9/0045 ,  G01L9/0054 ,  G01L15/00

Abstract: A pressure sensor (15) with double measuring scale, comprising: a flexible body (16, 34) designed to undergo deflection as a function of a said pressure (P); piezoresistive transducers (28, 29; 94) for detecting the deflection; a first focusing region (30) designed to concentrate, during a first operating condition, a first value (P INT1 ) of said pressure (P) in a first portion (19) of the flexible body (16, 34) so as to generate a deflection of the first portion (19) of the flexible body (16, 34); and a second focusing region (33) designed to concentrate, during a second operating condition, a second value (P INT2 ) of said pressure (P) in a second portion (17) of the flexible body (16, 34) so as to generate a deflection of the second portion (17) of the flexible body (16, 34). The piezoresistive transducers correlate the deflection of the first portion (19) of the flexible body (16, 34) to the first pressure value (P INT1 ) and the deflection of the second portion (17) of the flexible body (16, 34) to the second pressure value (P INT2 ).

Abstract translation: 的压力传感器（15）与双测量刻度，包括：柔性体（16，34）设计成经历偏转为所述压力（P）的函数; 压阻换能器（28，29; 94），用于检测所述偏转; 设计为浓缩物，在第一操作条件期间的第一聚焦区（30），在所述柔性主体（16，34）的第一部分（19）的第一值，所述压力的（P INT1）（P），以便产生 柔性主体（16，34）的第一部分（19）的偏转; 并设计成集中，第二操作条件期间的第二聚焦区（33），第二个值的所述压力的（P INT2）（P）在所述柔性主体的第二部分（17）（16，34），以便 生成柔性主体（16，34）的第二部分（17）的偏转。 压阻传感器的柔性主体（16，34）的第一压力值（P INT1）和柔性主体的第二部分（17）的偏转的第一部分（19）的偏转相关（16，34） 到第二压力值（P INT2）。

公开(公告)号：EP2362328A1

公开(公告)日：2011-08-31

申请号：EP11155905.0

申请日：2011-02-24

Applicant: STMicroelectronics S.r.l.

Inventor： Pagani, Alberto ,  Finocchiaro, Alessandro ,  Girlando, Giovanni

IPC: G06K19/07 ,  H01Q1/52 ,  H01Q1/22 ,  G06K19/077

CPC classification number: H01Q1/2225 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  H01L21/268 ,  H01L21/67115 ,  H01L21/67253 ,  H01L22/26 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01Q1/526 ,  Y10T29/49004 ,  H01L2924/00

Abstract: An electronic communications device, including: a body (32) of semiconductor material defining at least one integrated electronic circuit and having a top surface (32a); an electromagnetic shield (36); a radiant element (42); and a capacitive element (C) formed by a first electrode (50) and a second electrode (52), the radiant element (42) being arranged on top of the top surface (32a) and being ohmically connected to the first electrode (50) and the second electrode (52) by means of a first connection element (54) and a second connection element (56), respectively, the electromagnetic shield (36) being arranged between the radiant element (42) and the top surface (32a) and forming at least the second electrode.