公开(公告)号：EP1296378A1

公开(公告)日：2003-03-26

申请号：EP01830599.5

申请日：2001-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Ponzio, Paola Maria

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L23/485 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712 ,  Y10S438/981

Abstract: A MOS technology semiconductor device formed on a substrate (1) of a first conductivity type is described. The device comprises zones (200) where elementary active units suitable for treating electric signals and at least one inactive zone (100, 101) suitable to the electric signal output or input are formed. The substrate (1) is connected with the drain terminal of said device and the elementary active units comprise body regions (23) of a second conductivity type which are connected with to the source terminal. The at least one inactive zone (100, 101) comprises a semiconductor region (4) of a second conductivity type which is formed in the substrate (1), which is adjacent with a surface of the substrate, which is connected with the source terminal of the device and placed under a conductive layer (7); the semiconductor region (4) is covered by a silicon oxide layer (2) which has a surface alternation of first (8) and second (5) zones which are contiguous to each other and wherein the first zones (8) have a higher thickness than the second zones (5) and the silicon oxide layer (2) is covered by a conductive layer (7).

Abstract translation: 描述形成在第一导电类型的衬底（1）上的MOS技术半导体器件。 该装置包括区域（200），其中形成适合于处理电信号的基本有源单元和形成适合于电信号输出或输入的至少一个非活动区域（100,101）。 衬底（1）与所述器件的漏极端子连接，并且基本有源单元包括与源极端子连接的第二导电类型的体区域（23）。 所述至少一个非活性区域（100,101）包括形成在所述基板（1）中的与所述基板的表面相邻的第二导电类型的半导体区域（4），所述半导体区域与所述源极端子 并放置在导电层（7）下方; 半导体区域（4）由氧化硅层（2）覆盖，氧化硅层（2）具有彼此邻接的第一（8）和第二（5）区域的表面交替，并且其中第一区域（8）具有较高的厚度 比第二区域（5）和氧化硅层（2）被导电层（7）覆盖。

公开(公告)号：EP1058315A1

公开(公告)日：2000-12-06

申请号：EP99830340.8

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/41

CPC classification number: H01L29/404 ,  H01L27/0629

Abstract: Semiconductor device for high voltages comprising at least one power component (21) and at least one edge termination (100). Said edge termination (100) comprises a voltage divider including a plurality of capacitors (C7, C8, C9, C10, C11, C12) in series, which are formed by couples of said capacitors (C7, C8, C9, C10, C11, C12) formed by metal layers (71; 72) of a first level and polysilicon layers (11) of a second level interposed from a dielectric layer (8) underlying said metal layers (71; 72). The metal layers (71; 72) are alternated to said polysilicon layers (11) but extend in part over a zone of said dielectric layer (8) superimposed on said polysilicon layers (11). The edge termination (100) is connected between non-driveable terminals of said power component (21).

Abstract translation: 用于高电压的半导体器件包括至少一个功率部件（21）和至少一个边缘终端（100）。 所述边缘终端（100）包括分压器，其包括串联的多个电容器（C7，C8，C9，C10，C11，C12），所述电容器由所述电容器（C7，C8，C9，C10，C11， 由第一级的金属层（71; 72）形成的第二层的第二层（11）和从第一层的介电层（8）介入的第二层的多晶硅层（11）形成。 金属层（71; 72）与所述多晶硅层（11）交替，但部分地跨越叠加在所述多晶硅层（11）上的所述介电层（8）的区域。 边缘终端（100）连接在所述功率部件（21）的不可驱动端子之间。

公开(公告)号：EP1058318A1

公开(公告)日：2000-12-06

申请号：EP99830339.0

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Grimaldi, Antonio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7811

Abstract: Semiconductor device for high voltages comprising at least one power component (21), e.g. a power MOSFET, and at least one edge termination (100). Said edge termination (100) comprises a voltage divider including a plurality of diode-connected MOS transistors (31;32;33;34) in series, said edge termination (100) being connected between current-carrying, main terminals of said power component (21).

Abstract translation: 用于高电压的半导体器件包括至少一个功率部件（21），例如， 功率MOSFET和至少一个边缘终端（100）。 所述边缘终端（100）包括一个分压器，包括串联的多个二极管连接的MOS晶体管（31; 32; 33; 34），所述边缘终端（100）连接在所述功率部件的载流主端子 （21）。

公开(公告)号：EP1058318B1

公开(公告)日：2008-04-16

申请号：EP99830339.0

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Grimaldi, Antonio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7811

公开(公告)号：EP0782201B1

公开(公告)日：2000-08-30

申请号：EP95830542.7

申请日：1995-12-28

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L29/417 ,  H01L23/482 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41725 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a semiconductor material layer (3) of a first conductivity type. The elementary functional units comprise body stripes (9;90) of a second conductivity type extending substantially parallely to each other and source regions (14;140) of the first conductivity type. A conductive gate layer (17;170) is insulatively disposed over the semiconductor material layer (3) between the body stripes (9;90). A mesh (4;40) of the second conductivity type is formed in the semiconductor material layer (3) and comprises an annular frame region (5;50) surrounding the plurality of body stripes (9;90) and at least one first elongated stripe (7;60) extending within the annular frame region (5;50) in a direction substantially orthogonal to the body stripes (9;90) and merged with the annular frame region (5;50), the body stripes (9;90) being divided by the first elongated stripe (7;60) in two respective groups and being merged with the mesh (4;40). A conductive gate finger (25;250) connected to said conductive gate layer (17;170) insulatively extends over the first elongated stripe (7;60). Source metal plates (20;200) are provided covering each group of parallel body stripes and contacting each body stripe of the group. The conductive gate finger (25;250) is covered and contacted by a respective metal gate finger (27;270).

公开(公告)号：EP1408552A1

公开(公告)日：2004-04-14

申请号：EP02425611.7

申请日：2002-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Ponzio, Paola

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/0696 ,  H01L29/41758 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7835

Abstract: A semiconductor integrated device of the MOS type comprising a substrate (1, 2) of a first conductivity type is described. The substrate (1) comprising a plurality of active zones (300; 301) and inactive zones; the active zones (300; 301) comprise elementary MOS cells of said semiconductor device which are alternated to a plurality of separation zones (31). Each one of the elementary MOS cells comprises at least one source region (8), at least one drain region (7) and at least one gate structure (4, 5); said at least one gate structure (4, 5) comprises at least one first conductor material finger (5). The device comprises first metal stripes (50; 55) adapted for contacting said source regions (8) of the active zones (300; 301), second metal stripes (110, 11) adapted for contacting the drain regions (7) and third metal stripes (60) placed on the inactive zones and adapted for contacting said at least one conductor material finger (5) of each elementary cell by forming a contact point (Q) formed by a first prolongation of said at least one finger (5) for connecting with one of said third stripes (60); the first metal stripes (50; 55), the second metal stripes (110, 11) and the third metal stripes (60) being placed on the substrate (1, 2) of semiconductor material substantially at the same level. At least one of said third metal stripes (60) comprises at least one fourth metal stripe (20) placed on one of said separation zones (31). At least one conductor material finger (5) of each elementary cell has at least one second prolongation (51; 52) and the at least one fourth metal stripe (20) has at least one first prolongation (21, 22) adapted for being placed on said at least one second prolongation (51; 52) of said at least one material conductor finger (5) to form at least another contact point (T; H).

Abstract translation: 半导体集成电路的金属氧化物半导体型的装置中，包括：第一金属条纹，第二金属条纹，和第三金属条纹，其中至少一个包括设置在分离区（一个或多个）第四金属条（多个）。 第四金属条（或多个）具有第一延长并放置在导体材料（多个）手指的第二延长（或多个）。 半导体集成电路的金属氧化物半导体（MOS）型的装置中，包括第一导电类型，其包括有源区（300）和所述半导体器件的非活性区的衬底; 第一金属条（50）的接触源极区和有源区; 第二金属条（110，11）的接触漏区; 通过对与第三中的一个连接形成由所述（多个）手指的第一延长形成的接触点（Q）放置在每个基本单元的非有源区和接触导体材料（多个）手指和第三金属条（60） 条纹。 有源区域包括半导体器件的基本MOS细胞并与分离区交替。 基本MOS单元的每一个包括源极区域（S），漏极区域（S），和栅极结构（S），其包括第一导体材料（多个）手指（5）。 第一金属条纹，第二金属条纹和第三金属条纹基本上在同一水平上放置半导体材料的基片。 至少第三金属条中的一个包括布置在分离区（一个或多个）第四金属条（或多个）（20）。 每个基本单元的导体材料（多个）手指具有第二延长（或多个）（51）。 第四金属条（或多个）具有第一延长（21）并放置在导体材料（多个）手指的第二延长（或多个），以形成至少另一个接触点（T）。 一个独立的claimsoft包括用于制造上的第一导电类型的半导体材料的基片，包括通过形成在基板内的第二导电类型的源极区形成有源区中的MOS类型的集成器件的工艺，漏的区域 第二导电类型，以及栅极结构，其包括导体材料层（一个或多个）时，栅极结构形成与源极区和漏极区，该装置的基本MOS细胞; 形成具有基本MOS单元交替分离区; 掩模和在所述半导体衬底上沉积一金属层，以形成用于接触所述源极区，用于接触所述漏极区域和第三金属条用于在点（Q）接触的栅极结构的每一导体材料层的第二金属条第一金属条纹; 以及在所述分离区和在其附近的用于沉积金属以形成第四金属条纹设有窗口的掩模并放置在导体材料以形成另一接触点（T）的第一延长。 掩模的形成和栅极结构的导体材料的沉积允许所述导体材料的第一次翻转的形成。

公开(公告)号：EP1058315B1

公开(公告)日：2003-08-27

申请号：EP99830340.8

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/41

CPC classification number: H01L29/404 ,  H01L27/0629