公开(公告)号：EP1422719A2

公开(公告)日：2004-05-26

申请号：EP03103920.9

申请日：2003-10-23

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  MICHELONI, Rino

IPC: G11C11/00

CPC classification number: G11C11/005

Abstract: A semiconductor memory comprises a plurality of memory cells (MC), for example Flash memory cells, arranged in a plurality of lines (LBL), and a plurality of memory cell access signal lines (MBL), each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance (CMBL) intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

Abstract translation: 半导体存储器包括布置在多行（LBL）中的多个存储单元（MC），例如闪存单元，以及多个存储单元存取信号线（MBL），每个存储单元与至少一个相应的存储单元 存储单元行，用于访问所述至少一个相应行的存储器单元的存储单元; 每个信号线具有与其本征相关联的电容（CMBL）。 提供了多个易失性存储单元，每个易失性存储单元均具有电容存储元件。 每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。 特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。

公开(公告)号：EP1426968A2

公开(公告)日：2004-06-09

申请号：EP03104384.7

申请日：2003-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： MICHELONI, Rino ,  RAVASIO, Roberto

IPC: G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454

Abstract: A method of programming an electrically programmable memory comprises applying at least one first programming pulse to a group of memory cells ( MC1-MCk ) of the memory, accessing the memory cells of the group to ascertain a programming state thereof, and applying at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.

Abstract translation: 一种编程电可编程存储器的方法包括将至少一个第一编程脉冲施加到存储器的一组存储器单元（MC1-MCK），访问该组的存储器单元以确定其编程状态，以及应用至少一个 第二编程脉冲到编程状态未被确定以对应于期望的编程状态的组中的那些存储器单元。 根据在所述至少一个第一编程脉冲之间的所述组中的存储器单元的偏置条件的预测变化，在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间改变施加到所述存储器单元的控制电极的电压 和至少一个第二编程脉冲。 因此避免了对存储器单元的不期望​​的过度编程。

公开(公告)号：EP1624462A1

公开(公告)日：2006-02-08

申请号：EP04103714.4

申请日：2004-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： CRIPPA, Luca ,  MICHELONI, Rino

IPC: G11C16/28 ,  G11C16/24 ,  G11C7/06 ,  G11C7/12 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

Abstract: A sensing circuit for sensing semiconductor memory cells ( MC,m ), comprising: at least one first circuit branch ( 120a ) adapted to be operatively coupled to a respective memory cell to be sensed, so as to be run through by a current ( I,m ) corresponding to a memory cell state; a feedback-controlled circuit element ( N41a ) in the first circuit branch, for controlling a memory cell access voltage; a current-to-voltage conversion circuit ( N41a ) in the first branch, adapted to convert said current into a correspondent converted voltage signal, indicative of the memory cell state, and at least one comparator ( 125 ) for comparing the converted voltage signal with a comparison voltage, for discriminating among at least two different states of the memory cell. The converted voltage signal corresponds to a control signal of the feedback-controlled circuit element.

Abstract translation: 一种用于感测半导体存储器单元（MC，m）的感测电路，包括：至少一个第一电路分支（120a），适于可操作地耦合到待感测的相应存储单元，以便通过电流（I ，m）对应于存储单元状态; 第一电路支路中的反馈控制电路元件（N41a），用于控制存储单元访问电压; 第一分支中的电流 - 电压转换电路（N41a），用于将表示存储单元状态的所述电流转换为相应的转换电压信号，以及至少一个比较器（125），用于将转换后的电压信号与 比较电压，用于区分存储器单元的至少两个不同状态。 转换后的电压信号对应于反馈控制电路元件的控制信号。

公开(公告)号：EP1422719A3

公开(公告)日：2005-04-27

申请号：EP03103920.9

申请日：2003-10-23

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  MICHELONI, Rino

IPC: G11C11/00

CPC classification number: G11C11/005

Abstract: A semiconductor memory comprises a plurality of memory cells (MC), for example Flash memory cells, arranged in a plurality of lines (LBL), and a plurality of memory cell access signal lines (MBL), each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance (CMBL) intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

公开(公告)号：EP1426968A3

公开(公告)日：2007-06-20

申请号：EP03104384.7

申请日：2003-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： MICHELONI, Rino ,  RAVASIO, Roberto

IPC: G11C11/56 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454

Abstract: A method of programming an electrically programmable memory comprises applying at least one first programming pulse to a group of memory cells ( MC1-MCk ) of the memory, accessing the memory cells of the group to ascertain a programming state thereof, and applying at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.

Abstract translation: 一种对电可编程存储器进行编程的方法包括将至少一个第一编程脉冲施加到存储器的一组存储器单元（MC1-MCk），访问该组的存储器单元以确定其编程状态，并且将至少一个 第二编程脉冲到编程状态未被确定为对应于期望的编程状态的组中的那些存储器单元。 施加到存储器单元的控制电极的电压在至少一个第一编程脉冲和至少一个第二编程脉冲之间根据组中的存储器单元的偏置条件的预测变化在所述至少一个第一编程脉冲 和至少一个第二编程脉冲。 因此避免了对存储单元的不希望的过度编程。

公开(公告)号：EP1422719B1

公开(公告)日：2009-04-08

申请号：EP03103920.9

申请日：2003-10-23

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  MICHELONI, Rino

IPC: G11C11/00

CPC classification number: G11C11/005

公开(公告)号：EP1591858A1

公开(公告)日：2005-11-02

申请号：EP04101718.7

申请日：2004-04-26

Applicant: STMicroelectronics S.r.l.

Inventor： CRIPPA, Luca ,  SANGALLI, Miriam ,  SCOMMEGNA, Salvatrice ,  MICHELONI, Rino

IPC: G05F3/30

CPC classification number: G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit - IC - (100) comprising a first (115a) and at least one second functional blocks (115b,...,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b,...,Vrg,n) are respectively associated. The trimming structure comprises respective trimmable circuit structures (205a,210a,...,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage means (110) for storing trimming configurations for the trimmable circuit structures. The trimming configuration storage means are such that a change in the trimming configuration for the trimmable circuit structure of the first functional block causes a corresponding change in the trimming configuration for the trimmable circuit structure of the at least one second functional block. In addition, the trimmable circuit structures are such that a change in the at least one second IC functional parameter in response to the corresponding change in the trimming configuration for the trimmable structure of the at least one second functional block is proportional to the change in the first IC functional parameter consequent to the change in the trimming configuration for the trimmable circuit structure of the first functional block.

Abstract translation: 一种微调结构，用于微调包括第一功能块（115a）和至少一个第二功能块（115b，...，115n）的集成电路-IC-（100）的功能参数，其中第一功能块（Vrg，a） 至少一个第二IC功能参数（Vrg，b，...，Vrg，n）分别相关联。 修剪结构包括第一功能块和至少一个第二功能块中包括的各个可修整电路结构（205a，210a，...，205n，210n），以及修整配置存储装置（110），用于存储可修剪电路结构 。 修整配置存储装置使得第一功能块的可修整电路结构的修整配置的改变引起修整配置的相应改变，用于至少一个第二功能块的可修整电路结构。 此外，所述可调整电路结构使得响应于所述至少一个第二功能块的可调整结构的调整配置的对应改变而改变所述至少一个第二IC功能参数与所述至少一个第二功能参数 第一IC功能参数是由于第一功能块的可微调电路结构的微调配置的变化而引起的。