公开(公告)号：EP1912121A1

公开(公告)日：2008-04-16

申请号：EP06425632.4

申请日：2006-09-13

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

IPC: G06F11/10 ,  G06F11/20

CPC classification number: G11C29/82 ,  G06F11/1068 ,  G11C29/24 ,  G11C2029/0411

Abstract: Basic redundancy information is non volatily stored in a reserved area (that is an area of the array that is not addressable by the user of the device) of the addressable area of the array and is copied on volatile storage supports at every power-on of the memory device.
The unpredictable though statistically inevitable presence of fail array elements also in such a reserved area of the memory array that would corrupt the basic redundancy information as established during the test-on wafer (EWS) phase of the fabrication process and thus increasing the number of rejects, lowering the yield of the fabrication process, is effectively overcome by writing the basic redundancy data in the reserved area of the array with an ECC technique, using a certain error correction code that may be chosen among so-called majority codes 3, 5, 7, 15 and the like or Hamming code for 1, 2, 3 or more errors, in function of the fail probability of a memory cell as determined by the testing on wafer of the devices during fabrication (fail probability of the specific fabrication process used).
A significant area saving is achieved compared to the use of fuse arrays and other known approaches.

Abstract translation: 基本冗余信息不会被浪费地存储在阵列的可寻址区域的保留区域（即阵列的不能由设备的用户可寻址的区域）中，并且在每次上电时复制到易失性存储器支持 存储设备。 在存储器阵列的这种保留区域中，不可预测的存在故障阵列元件的不可避免的存在将损坏在制造过程的测试晶片（EWS）阶段期间建立的基本冗余信息，从而增加了拒绝数量 通过使用可以在所谓的多数代码3,5中选择的某个纠错码，使用ECC技术将基本冗余数据写入阵列的保留区域中，有效地克服了降低制造处理的产量， 7,15等等或Hamming代码用于1,2,3或更多的错误，其功能是通过在制造期间在器件的晶片上的测试（使用特定制造过程的故障概率）确定的存储器单元的故障概率 ）。 与使用保险丝阵列和其他已知方法相比，实现了显着的面积节省。

公开(公告)号：EP1912121B1

公开(公告)日：2009-08-12

申请号：EP06425632.4

申请日：2006-09-13

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

IPC: G06F11/10 ,  G06F11/20

CPC classification number: G11C29/82 ,  G06F11/1068 ,  G11C29/24 ,  G11C2029/0411

公开(公告)号：EP1612950A1

公开(公告)日：2006-01-04

申请号：EP04425486.0

申请日：2004-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/1555 ,  H03M13/152 ,  H03M13/6561

Abstract: The invention relates to a method and system for correcting errors in multilevel memories, both of the NAND and of the NOR type. The method provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. Two possible solutions are shown.
The parallelism being used for blocks C, 1 and 3 can be chosen in order to optimise the system performances in terms of latency and device area.

Abstract translation: 本发明涉及一种方法和系统，用于多级存储器校正错误，这两种类型的NAND和NOR。 该方法提供使用的BCH纠错码由编码和解码架构，允许现有技术解决方案的顺序的延迟限制的方式作出平行于被克服。 两种可能的解决方案中。 正在使用的并行用于块C，1和3可以以优化系统性能的延迟和设备面积方面进行选择。

公开(公告)号：EP1460765A1

公开(公告)日：2004-09-22

申请号：EP03425172.8

申请日：2003-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Lunelli, Massimiliano ,  Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

IPC: H03M13/13 ,  H03M13/15 ,  H03M13/19

CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

Abstract: A method for making error corrections on digital information coded as symbol sequences ( x ), for example digital information stored in electronic memory systems or transmitted from and to these systems is described, providing the transmission of sequences ( x ) incorporating a portion of error corrector code allowing the sequence ( x ) which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received.
Advantageously according to the invention, the error code incorporated in the original sequence ( x ) belongs to a non Boolean group.

Abstract translation: 描述了用于对编码为符号序列（x）的数字信息进行纠错的方法，例如存储在电子存储器系统中或从这些系统发送的数字信息，或从这些系统发送和传送到这些系统的方法，提供包含错误校正器的一部分的序列（x） 允许更可能是通过使用奇偶校验矩阵计算误差校正子传送的序列（x）的序列（x），以便在接收时恢复。 有利地，根据本发明，并入原始序列（x）中的错误代码属于非布尔组。

公开(公告)号：EP1830269B1

公开(公告)日：2009-05-13

申请号：EP06425141.6

申请日：2006-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

公开(公告)号：EP1830269A1

公开(公告)日：2007-09-05

申请号：EP06425141.6

申请日：2006-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A 0 , A 1 , ..., A LS-1 ) to generate a first recovered string (S 1 ), and performing a first decoding attempt using the first recovered string (S 1 ). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S 2 -S N ) is generated. On the basis of a comparison between the first recovered string (S 1 ) and the second recovered string (S 2 -S N ), a modified string (S M ) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (S M ).

Abstract translation: 用于与错误校正编码的存储器装置的读出方法设想如下步骤：执行的存储器位置处的多个第一读取（A 0，A 1，...，A LS-1），以产生一个第一回收串 （S 1），并执行使用第一回收串（S 1）的第一解码尝试。 当第一解码尝试失败，存储器位置被读取的至少一个第二时间，并且至少一个第二回收串（S 2 -S N）被产生。 在第一回收串（S 1）和所述第二回收串（S 2 -S N）之间的比较的基础上，产生一个修改后的字符串（SM），其中擦除（X）的位置，和至少一个第二 解码尝试是使用修改后的字符串（SM）。

公开(公告)号：EP1612949A1

公开(公告)日：2006-01-04

申请号：EP04425485.2

申请日：2004-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/3707 ,  H03M13/6502

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

Abstract translation: 本发明涉及一种使用二进制BCH码对多层存储器中的错误进行校正的方法和系统。 通过分析综合征成分估计误差数（5）。 如果估计误差的数量为1，则执行汉明码的简单解码。 否则，执行BCH码的常规解码（2,3）。 这避免了在仅存在一个错误的情况下计算错误定位器多项式及其根，并因此降低平均解码复杂度。