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    A memory device
    2.
    发明公开
    A memory device 有权
    Speicherordnung

    公开(公告)号：EP1647991A1

    公开(公告)日：2006-04-19

    申请号：EP04105094.9

    申请日：2004-10-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mirichigni, Graziano ,  Martinelli, Andrea

    IPC: G11C16/24

    CPC classification number: G11C16/24 ,  G11C16/0416 ,  G11C16/26

    Abstract: A semiconductor memory device (100) is disclosed. The semiconductor memory device includes a plurality of memory cells (110), arranged according to a plurality of rows and a plurality of column. The memory devices further includes a plurality of bit lines (BL1), each bit line being associated with a respective column of said plurality, and a selecting structure (130b) of the bit lines, to select at least one among said bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit (210, CL1, CL0, C 1 , C 2 ), adapted to causing the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

    Abstract translation: 公开了一种半导体存储器件（100）。 半导体存储器件包括根据多行和多列布置的多个存储单元（110）。 存储器件还包括多个位线（BL1），每个位线与所述多个的相应列相关联，以及位线的选择结构（130b），以选择所述位线中的至少一个，保持 剩余的位线未选择。 所述存储器件还包括钳位电路（210，CL1，CL0，C 1，C 2），其适用于在对所述存储器的访问操作期间使与所选位线相邻的未选定位线的规定电压的钳位 。

    A full-swing wordline driving circuit for a nonvolatile memory
    4.
    发明公开
    A full-swing wordline driving circuit for a nonvolatile memory 有权
    全电压摆幅字线驱动器的非易失性存储器

    公开(公告)号：EP1473738A1

    公开(公告)日：2004-11-03

    申请号：EP03425264.3

    申请日：2003-04-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Mirichigni, Graziano ,  Villa, Corrado

    IPC: G11C16/08 ,  G11C8/08

    CPC classification number: G11C8/08 ,  G11C16/08

    Abstract: A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

    Abstract translation: 一种电路（300）提出了一种用于驱动控制的非易失性存储器装置（100）中的至少一个存储单元（105）的存储器线（110），该电路响应于第一和第二选择信号，每一个 适合于采用第一逻辑值，或第二逻辑值，worin电路包括用于将第一选择信号转换成第一操作信号和用于第二选择信号转换为第二电平移位器（120克）第一电平移位器（120秒） 的第二操作信号，各电平移位器包括用于移动相应的选择信号的逻辑值中的一个到第一偏置电压的第一移位装置（210S，210克），以及用于将所述第一操作信号或第二选择器（140） 偏置电压施加到所述存储器线gemäß到所述第二操作信号; 在发明的电路中的每个电平移位器还包括第二移动装置（305S，305克），用于另一个相应的选择信号的逻辑值的转移到第二偏置电压。

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