公开(公告)号：EP1081477A1

公开(公告)日：2001-03-07

申请号：EP99830540.3

申请日：1999-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Matranga, Giovanni ,  Lo Coco, Luca ,  Compagno, Giuseppe

IPC: G01K7/01 ,  G01K3/00

CPC classification number: G01K3/005 ,  G01K7/01

Abstract: This invention relates to a CMOS technology temperature sensor of a type which comprises a first circuit portion (2) arranged to generate an electric voltage signal whose value increases with the temperature to be sensed, and a second circuit portion (3) arranged to generate an electric voltage signal whose value decreases with the temperature to be sensed. A comparator (4) is provided as an output stage for comparing the values of both voltage signals.
Advantageously, the generator element of the second circuit portion (3) is a vertical bipolar transistor connected in a diode configuration.

Abstract translation: 本发明涉及一种CMOS技术的温度传感器，它包括一个第一电路部分（2），该第一电路部分（2）被布置成产生一个电压信号，该电压信号的值随着待感测的温度而增加;以及第二电路部分（3） 其电压信号的值随着要感测的温度而降低。 提供比较器（4）作为用于比较两个电压信号的值的输出级。 有利地，第二电路部分（3）的发生器元件是以二极管配置连接的垂直双极晶体管。

公开(公告)号：EP2506434A1

公开(公告)日：2012-10-03

申请号：EP12162749.1

申请日：2012-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Ucciardello, Carmelo ,  Conte, Antonino ,  Matranga, Giovanni ,  Grasso, Rosario Roberto

IPC: H03K17/10 ,  H03K3/356

CPC classification number: H03K17/102 ,  H03K3/356113

Abstract: A biasing circuit (10; 10') has: an input designed to receive a supply voltage (Vi), a value of which is higher than a limit voltage (Vdd); a control stage (12; 12'), generating a first control signal (P gL ; N gL ) and a second control signal (P gR ; N gR ), with mutually complementary values, equal alternatively to a first value (Vi), in a first half-period of a clock signal, or to a second value (Vi - Vdd; Vi + Vdd), in a second half-period of the clock signal, the first and second values being a function of the supply voltage (Vi) and of the limit voltage (Vdd); and a biasing stage (16; 16'), which generates on an output a biasing voltage (V cp ; V cn ), as a function of the values of the first control signal (P gL ; N gL ) and of the second control signal (P gR ; N gR ). The first and second control signals are designed to control transfer transistors, for transferring the supply voltage (Vi) to respective outputs, whilst the biasing voltage is designed to control protection transistors in order to prevent overvoltages on the transfer transistors.

Abstract translation: 偏置电路（10; 10'）具有：设计成接收电压高于极限电压（Vdd）的电源电压（Vi）的输入端; 控制级（12; 12'），产生与第一值（Vi）相等的互补值的第一控制信号（P gL; N gL）和第二控制信号（P gR; N gR） 在时钟信号的第一半个周期中，或者在时钟信号的第二个半周期中为第二值（Vi-Vdd; Vi + Vdd），第一和第二值是电源电压的函数 Vi）和极限电压（Vdd）; 以及偏置级（16; 16'），其在输出上产生作为所述第一控制信号（P gL; N gL）和所述第二控制的值的函数的偏置电压（V cp; V cn） 信号（P gR; N gR）。 第一和第二控制信号被设计成控制传输晶体管，用于将电源电压（Vi）传送到相应的输出，同时偏置电压被设计成控制保护晶体管，以防止转移晶体管上的过电压。

公开(公告)号：EP1081477B1

公开(公告)日：2006-10-18

申请号：EP99830540.3

申请日：1999-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Matranga, Giovanni ,  Lo Coco, Luca ,  Compagno, Giuseppe

IPC: G01K7/01 ,  G01K3/00

CPC classification number: G01K3/005 ,  G01K7/01

公开(公告)号：EP2166656A1

公开(公告)日：2010-03-24

申请号：EP08425608.0

申请日：2008-09-18

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Ucciardello, Carmelo ,  Matranga, Giovanni

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/077

Abstract: The invention relates to a charge pump latch circuit (10) comprising at least one first and one second charge pump stage (CBi-1, CBi) interconnected in an intermediate circuit node (INT) and a stabilization stage (20) connected to the intermediate circuit node (INT) and to control terminals of transistors comprised in the first and second charge pump stages (CBi-1, CBi).
Advantageously according to the invention, the stabilisation stage (20) is connected to at least one first and one second pair (CFO1, CFO2) of first and second enable terminals receiving suitable and distinct phase signals able to ensure the turn-off of the stabilisation stage (20) during the overlapping periods of the phase signals.

Abstract translation: 本发明涉及一种连接到中间电荷泵闩锁电路（10），包括至少一个第一和一个第二电荷泵级（CB I-1，CBⅰ）在中间电路节点（INT）相互连接和稳定阶段（20） 电路节点（INT），并控制在所述第一和第二电荷泵级包括晶体管的端子（CB I-1，CB i）中。 有利的是雅丁到本发明，该稳定化级（20）被连接到第一中的至少一个第一和一个第二对（CFO1，CFO2）和第二使能接收能够确保稳定的关断适当的和不同的相位信号端子 级（20）中的相位信号的重叠周期。

公开(公告)号：EP1881588A1

公开(公告)日：2008-01-23

申请号：EP06425495.6

申请日：2006-07-19

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Ucciardello, Carmelo ,  D'Alessandro, Carmine ,  Miccichè, Mario ,  Matranga, Giovanni ,  De Costantini, Diego

IPC: H02M3/07 ,  G11C5/14 ,  G11C16/30

CPC classification number: H02M3/073 ,  G11C5/145 ,  G11C16/12 ,  H02M3/07

Abstract: A charge pump architecture (10) is described of the type comprising at least one first pump (11) for the generation of a first working voltage (VXR), a second pump (12) for the generation of a second working voltage (VYP) and a third pump (13) for the generation of a third working voltage (VNEG).
Advantageously according to the invention, the first pump (11) is connected to an internal supply voltage reference (Vdd) having limited value and has an output terminal (OUT1) connected to the second and third pumps (12,13) and supplying them with the first working voltage (VXR) as supply voltage.
A method is also described for managing the generation of voltages to be used together with the charge pump architecture (10) according to the invention.

Abstract translation: 描述了包括用于产生第一工作电压（VXR）的至少一个第一泵（11），用于产生第二工作电压（VYP）的第二泵（12））的类型的电荷泵结构（10） 以及用于产生第三工作电压（VNEG）的第三泵（13）。 有利地，根据本发明，第一泵（11）连接到具有有限值的内部电源电压基准（Vdd），并且具有连接到第二和第三泵（12,13）的输出端子（OUT1），并将它们提供给 第一工作电压（VXR）作为电源电压。 还描述了一种用于管理与根据本发明的电荷泵结构（10）一起使用的电压的产生的方法。