公开(公告)号：WO2010076187A3

公开(公告)日：2010-07-08

申请号：PCT/EP2009/067156

申请日：2009-12-15

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: H01L23/66 ,  H01L23/48 ,  H01L21/66 ,  H01L23/544 ,  H01L25/065

Abstract: An integrated electronic device (1) having a body (9) of semiconductor material and a first antenna (3;3a) which enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna (3b,3c). The integrated electronic device (1) has a first via (4;4a- 4d;50;50a;53) of magnetic material arranged at least in part inside the body (9), which forms, in use, a communication channel between the first antenna (3;3a) and the further antenna (3b,3c).

公开(公告)号：WO2010046724A1

公开(公告)日：2010-04-29

申请号：PCT/IB2008/003660

申请日：2008-10-22

Applicant: STMICROELECTRONICS (GRENOBLE) SAS ,  STMICROELECTRONICS S.R.L. ,  TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

Inventor： TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

IPC: G05B19/418 ,  G01R31/28

CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

Abstract: The invention relates to a method for an improved checking of repeatability and reproducibility of a measuring chain, in particular for the quality control by means of the semiconductor device testing, wherein testing steps are provided for multiple and different devices to be subjected to measurement through a measuring system comprising at least one concatenation of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement. Advantageously, the method comprises the following steps: checking repeatability and reproducibility of each type of unit that forms part of the measuring chain of the concatenation; then making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement.

Abstract translation: 本发明涉及一种用于改进测量链的重复性和再现性检查的方法，特别是通过半导体器件测试进行质量控制的方法，其中为多个和不同的器件提供测试步骤以通过 测量系统包括测试装置（ATE）和待测量的每个装置之间的测量单元的至少一个级联。 有利地，该方法包括以下步骤：检查构成级联测量链的一部分的每种类型的单元的重复性和重复性; 然后在各测量链之间进行整体的相关性，以检查重复性和再现性，使用相应的测量装置。

公开(公告)号：WO2012019768A1

公开(公告)日：2012-02-16

申请号：PCT/EP2011/004030

申请日：2011-08-11

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: G06K19/073

CPC classification number: G06K7/00 ,  G06K7/10178 ,  G06K19/025 ,  G06K19/072 ,  G06K19/07327 ,  G06K19/07336 ,  G06K19/07735 ,  G06K19/07756 ,  G06K19/07771 ,  G06K19/07775 ,  G06K19/07779

Abstract: The invention relates to a security system comprising at least one integrated circuit (24a) and a transceiver / transponder circuit (30), the at least one integrated circuit (24a) being provided with an antenna (36) for communicating with the transceiver / transponder circuit (30), an inhibiting element (24b, 44, 44a, 44b) being associated with the at least one integrated circuit (24a) for inhibiting communications with the transceiver / transponder circuit (30) and for securing the data contained in the at least one integrated circuit (24a). Advantageously, the inhibiting element (24b, 44, 44a, 44b) is an electromagnetic inhibiting element, the security system further comprising a coupling element (22) that is associated with the antenna (36) of the at least one integrated circuit (24a) for temporarily deactivating the electromagnetic inhibiting element (24b, 44, 44a, 44b) to allow communications between the at least one integrated circuit (24a) and the transceiver / transponder circuit (30).

Abstract translation: 本发明涉及一种包括至少一个集成电路（24a）和收发器/应答器电路（30）的安全系统，所述至少一个集成电路（24a）设置有天线（36），用于与收发器/应答器 电路（30），与所述至少一个集成电路（24a）相关联的禁止元件（24b，44,44a，44b），用于禁止与所述收发器/应答器电路（30）的通信并且用于保护包含在所述收发器/ 至少一个集成电路（24a）。 有利地，禁止元件（24b,44,44a，44b）是电磁抑制元件，所述安全系统还包括与所述至少一个集成电路（24a）的天线（36）相关联的耦合元件（22） 用于临时停用所述电磁抑制元件（24b,44,44a，44b）以允许所述至少一个集成电路（24a）与所述收发器/应答器电路（30）之间的通信。

公开(公告)号：WO2010015388A1

公开(公告)日：2010-02-11

申请号：PCT/EP2009/005655

申请日：2009-08-05

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/58 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

Abstract translation: 本发明涉及用于在电子或电磁测试（例如EMWS或EWS或WLBI测试）中并行供电的电路架构，每个电子设备（2）均集成在相同的半导体晶片（1）上，其中 电子器件（1）通过积分技术整齐地设置在半导体晶片（1）上并且具有由分隔划线（7）限定的边缘（5）。 有利地，根据本发明，电路架构包括： - 至少一个导电栅格（4），其将至少一组电子设备（2）互连并且具有到该组的设备的外部（14）的部分，以及 部分是内部（13）到组的装置; 导电栅格（4）的外部部分（14）也沿着分隔划线（7）延伸; 所述内部部分（13）在所述组的装置的至少一部分内延伸; 在外部部分（14）和导电栅格（4）的内部部分（13）之间的互连焊盘（6）设置在该组的至少一部分器件上，互连焊盘（6）连同 内部和外部部分，该组的不同电子设备（2）共同的电源线。

公开(公告)号：WO2014006570A8

公开(公告)日：2014-01-09

申请号：PCT/IB2013/055430

申请日：2013-07-02

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MOTTA, Alessandro ,  LOI, Sara

IPC: G02B6/12 ,  G02B6/43

Abstract: An integrated electronic device, delimited by a first surface (S 1 ) and by a second surface (S 2 ) and including: a body (2) made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector (30) and an emitter (130); and an optical path (OP), which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

公开(公告)号：WO2013128348A2

公开(公告)日：2013-09-06

申请号：PCT/IB2013/051422

申请日：2013-02-21

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto

CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L24/24 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A base (2) carries a first chip (3) and a second chip (4) oriented differently with respect to the base and packaged in a package (6). Each chip integrates an antenna and a magnetic via (13). A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips (3, 4) even if the magnetic path is interrupted, and is formed by a first stretch (5c) coupled between the first magnetic-coupling element (13) of the first chip and the first magnetic-coupling element (12) of the second chip, and a second stretch (5f) coupled between the second magnetic-coupling element (12) of the first chip and the second magnetic-coupling element (13) of the second chip. The first stretch has a parallel portion (5c1, 5c3) extending parallel to the faces (2a, 2b) of the base. The first and second stretches have respective transverse portions (5i1, 5i2) extending on the main surfaces of the second chip, transverse to the parallel portion.

Abstract translation: 基座（2）承载相对于基座不同定向并封装在封装（6）中的第一芯片（3）和第二芯片（4）。 每个芯片集成天线和磁通（13）。 磁耦合路径连接芯片，形成磁路，即使磁路被中断也能够在芯片（3,4）之间传递信号和电力，并且通过耦合在第一磁性体之间的第一拉伸（5c）形成 第一芯片的耦合元件（13）和第二芯片的第一磁耦合元件（12）以及耦合在第一芯片的第二磁耦合元件（12）和第二芯片之间的第二拉伸（5f） 第二芯片的磁耦合元件（13）。 第一拉伸具有平行于基部的表面（2a，2b）延伸的平行部分（5c1,5c3）。 第一和第二延伸部具有横向于平行部分的在第二芯片的主表面上延伸的相应横向部分（5i1,5i2）。

公开(公告)号：WO2014155348A1

公开(公告)日：2014-10-02

申请号：PCT/IB2014/060249

申请日：2014-03-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MURARI, Bruno

IPC: G01N27/22

CPC classification number: G01N27/223 ,  G01N17/04

Abstract: An integrated electronic device 1 for detecting at least one parameter related to humidity and/or presence of water and/or acidity/basicity of an environment surrounding the device is described. Such device 1 comprises a separation layer 14 from the surrounding environment, comprising at least one portion of insulating material 14, and further comprises a first conductive member 11 and a second conductive member 12, made of an electrically conductive material, arranged inside the separation layer 14, with respect to the surrounding environment, and separated from the surrounding environment by the separation layer 14. The device 1 also comprises a measurement module 15, having two measurement terminals 151, 152, electrically connected with the first 11 and the second 12 conductive members, respectively; the measurement module 15 is configured to provide an electric potential difference between the first 11 and the second 12 conductive members. The device 1 further comprises electrode means 13, configured to act as an electrode, arranged outside of the separation layer 14, with respect to the first 11 and the second 12 conductive members; the electrode means 13 are arranged so as to form, with the first 11 and the second 12 conductive members, an electromagnetic circuit having an electromagnetic circuit overall impedance variable based upon the exposure to environmental conditions with a variable level of humidity and/or acidity/basicity. The measurement module 15 is configured to measure the electromagnetic circuit overall impedance, which is present between the measurement terminals 151, 152, and to determine the at least one parameter to be detected, based on the overall impedance measured.

Abstract translation: 描述了用于检测与湿度和/或水的存在和/或设备周围环境的酸度/碱度相关的至少一个参数的集成电子设备1。 这种装置1包括与周围环境的分离层14，其包括绝缘材料14的至少一部分，并且还包括布置在分离层内部的由导电材料制成的第一导电构件11和第二导电构件12 14，相对于周围环境，并且通过分离层14与周围环境分离。装置1还包括测量模块15，其具有两个测量端子151,152，与第一11和第二导电12电连接 成员分别; 测量模块15被配置为提供第一11和第二导电构件12之间的电位差。 装置1还包括电极装置13，其被配置为相对于第一11和第二导电构件作为布置在分离层14外侧的电极; 电极装置13被布置成与第一11和第二12导电构件形成电磁电路，该电磁电路具有基于暴露于具有可变湿度和/或酸度/湿度的环境条件的总体阻抗变化， 碱性。 测量模块15被配置为基于测量的总阻抗来测量存在于测量端子151,152之间的电磁回路总阻抗，并且确定要检测的至少一个参数。

公开(公告)号：WO2014049537A1

公开(公告)日：2014-04-03

申请号：PCT/IB2013/058852

申请日：2013-09-25

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  ZIGLIOLI, Federico Giovanni

IPC: H05K1/02

CPC classification number: G01L1/005 ,  G01N33/38 ,  H05K1/0239 ,  H05K1/0278 ,  H05K1/189 ,  H05K2201/09081 ,  H05K2201/10098 ,  H05K2201/10151 ,  Y10T156/1051

Abstract: A planar electric circuit board may include a planar support of a foldable material defining a base surface and wings coupled to the base surface along respective folding lines so that the wings, when folded along the folding lines, are erected with respect to the base surface and remain in that position. An auxiliary circuit is on the planar support and may include pairs of capacitive coupling plates defined on the wings and on the base surface, and electric communication lines coupled to corresponding ones of the pairs of capacitive coupling plates.

Abstract translation: 平面电路板可以包括限定基部表面的可折叠材料的平面支撑件和沿着各个折叠线连接到基座表面的翼片，使得当沿着折叠线折叠时的翼片相对于基部表面竖立，并且 保持在这个位置。 辅助电路在平面支撑件上，并且可以包括限定在翼部和基部表面上的成对的电容耦合板，以及耦合到成对的电容耦合板中的对应的电气通信线。

公开(公告)号：WO2013174946A1

公开(公告)日：2013-11-28

申请号：PCT/EP2013/060669

申请日：2013-05-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MURARI, Bruno ,  ZIGLIOLI, Federico Giovanni ,  RONCHI, Marco ,  RICOTTI, Giulio

IPC: G01D11/24 ,  G01M5/00

CPC classification number: G01D11/245 ,  B28B23/0031 ,  G01K17/00 ,  G01L1/18 ,  G01M5/00 ,  G01N33/383

Abstract: A package (15) for devices (100) insertable into a solid structure (300) for detecting and monitoring one or more local parameters is described. The package (15) is made of a building material formed of particles of micrometric or sub-micrometric dimensions. A device (100) for detecting and monitoring one or more local parameters within a solid structure is further described. The device (100) comprises an integrated detection module (1), having at least one integrated sensor (10), and a package (15), having the above-mentioned characteristics, so arranged as to coat at least one portion of the device (100), comprising the integrated detection module (1). A method for manufacturing the device (100), and a system (200) for monitoring parameters in a solid structure (300), comprising such a device (100), are also described.

Abstract translation: 描述了可插入到用于检测和监视一个或多个局部参数的实体结构（300）中的装置（100）的封装（15）。 包装（15）由由微米或亚微米尺寸的颗粒形成的建筑材料制成。 进一步描述用于检测和监视固体结构内的一个或多个局部参数的装置（100）。 装置（100）包括具有至少一个集成传感器（10）的集成检测模块（1）和具有上述特征的封装（15），其被布置成涂覆该装置的至少一部分 （100），包括所述集成检测模块（1）。 还描述了用于制造装置的方法（100），以及用于监视包括这种装置（100）的实体结构（300）中的参数的系统（200）。

公开(公告)号：WO2014155326A2

公开(公告)日：2014-10-02

申请号：PCT/IB2014/060203

申请日：2014-03-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto

IPC: G01L25/00

CPC classification number: G01L1/142 ,  G01L1/144 ,  G01L1/148 ,  G01L1/26 ,  G01L25/00

Abstract: The invention relates to an integrated electronic device (400; 400a; 500, 500'; 600, 600'; 700, 700') on a semiconductor material chip for detecting the pressure related to a force (F) applied in a predetermined direction (d) within a solid structure. The device comprises: - an integrated element (51) defined by an operating surface of the chip (52) that is substantially orthogonal to the direction (d) of application of the force; first (53) and second (54) conductive elements accommodated within the substrate element (51) and configured to face the operating surface; a measure module (55) accommodated within the substrate element and comprising first (56) and second (57) measurement terminals which are electrically connected to the first (53) and second (54) conductive elements, respectively; a detecting element (58) arranged in the predetermined direction (d) such that the operating surface (52) is sandwiched between the first (53) and second (54) conductive elements and this detecting element ( 58 ); - an insulating layer (59) suitable to coat at least the operating surface in order to galvanically insulate the first (53) and second (54) conductive elements. The device comprises a layer of dielectric material (510, 510') which is at least sandwiched between the detecting element (58) and the insulating layer (59). The layer of dielectric material is elastically deformable following the application of the force (F) in the predetermined direction to change an electromagnetic coupling between the detecting element (58) and the above-mentioned first (53) and second (54) conductive elements.

Abstract translation: 本发明涉及一种半导体材料芯片上的集成电子设备（400; 400a; 500,500'; 600,600'; 700,700'），用于检测与沿预定方向施加的力（F）相关的压力 d）在固体结构内。 该装置包括：由芯片（52）的操作表面限定的与施加力的方向（d）基本正交的集成元件（51）; 第一（53）和第二（54）导电元件，其容纳在所述衬底元件（51）内并被配置为面对所述操作表面; 测量模块（55），其容纳在所述衬底元件内并且包括分别电连接到所述第一（53）和第二（54）导电元件的第一测量端子（56）和第二测量端子（57） 沿预定方向（d）布置的检测元件（58），使得操作表面（52）夹在第一（53）和第二（54）导电元件和该检测元件（58）之间; - 绝缘层（59），其适于至少涂覆所述操作表面以使所述第一（53）和第二（54）导电元件电绝缘。 该装置包括至少夹在检测元件（58）和绝缘层（59）之间的电介质材料层（510,510'）。 介电材料层可以沿预定方向施加力（F）而弹性变形，以改变检测元件（58）和上述第一（53）和第二（54）导电元件之间的电磁耦合。