公开(公告)号：EP1863089A1

公开(公告)日：2007-12-05

申请号：EP06425371.9

申请日：2006-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Piazza, Fausto ,  Vigiani, Carlo ,  Zabberoni, Paola

IPC: H01L27/105 ,  H01L27/02 ,  H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11534

Abstract: A method is described for manufacturing electrically non active structures of an integrated electronic circuit (1) formed on a semiconductor substrate (7) comprising first electrically active structures (2) which comprise electric components provided with conductive elements (16) of a first height (H1) projecting from said semiconductor substrate (7) and second electrically active structures (3) which comprise electric components provided with conductive elements (20) of a second height (H2) projecting from said semiconductor substrate (7), said first height being different from said second height, the method comprising the steps of:
- introducing, into the integrated electronic circuit (1), electrically non active structures (4) to superficially uniform the integrated electronic circuit (1),
- identifying, between the electrically non active structures (4), a first group (5) of electrically non active structures which is formed by those electrically non active structures comprised in areas (5a) which substantially extend for a predetermined radius (R) around each electric component belonging to the second electrically active structures (3),
- identifying, between the electrically non active structures (4), a second group (6) of electrically non active structures comprising electrically non active structures not belonging to the first group (5) of electrically non active structures,
- forming the electrically non active structures belonging to the first group (5) of electrically non active structures with elements (20a) projecting from the substrate (7) having a height equal to the second height (H2),
- forming the electrically non active structures belonging to the second group (6) of electrically non active structures with elements (16a) projecting from the substrate (7) having a height equal to the first height (H1), the elements (16a, 20a) belonging to the first (5) and second group (6) of electrically non active structures being formed by means of respective photolithographic steps.

Abstract translation: 描述了一种用于制造形成在半导体衬底（7）上的集成电子电路（1）的非电活动结构的方法，所述电子电路包括第一电活性结构（2），所述第一电活性结构（2）包括设置有第一高度的导电元件（16） H1）和第二电活动结构（3），所述第二电活性结构（3）包括设置有从所述半导体衬底（7）突出的第二高度（H2）的导电元件（20）的电气部件，所述第一高度不同 从所述第二高度，所述方法包括以下步骤：将集成电子电路（1）引入电非活动结构（4）以使所述集成电子电路（1）表面均匀; - 识别所述电非活动 结构（4），由非电活性结构组成的第一组（5），由非电活性结构构成 围绕属于第二电活动结构（3）的每个电气部件围绕预定半径（R）延伸的区域（5a）， - 识别在电非活性结构（4）之间的电子非活性结构（4）的第二组（6） 非活性结构包括不属于电非活性结构的第一组（5）的非电活性结构， - 形成属于电非活性结构的第一组（5）的非电活性结构，其中元件（20a）从 所述衬底（7）具有等于所述第二高度（H2）的高度， - 形成属于所述第二组（6）的电非活性结构的电非活性结构，其中从所述衬底（7）突出的元件（16a） 属于第一高度（H1）的高度，属于非活性结构的第一组（5）和第二组（6）的元件（16a，20a）通过相应的ph形成 光刻步骤。

公开(公告)号：EP1139419A1

公开(公告)日：2001-10-04

申请号：EP00830236.6

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Peschiaroli, Daniela ,  Maurelli, Alfonso ,  Palumbo, Elisabetta ,  Piazza, Fausto

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: Method of manufacturing an integrated circuit comprising a memory operating at high voltage and logic circuitry operating at a lower voltage than the memory:
   formation of a first layer of gate oxide (3) with a first thickness on first and second portions of a semiconductor substrate (1) which are intended, respectively, for first transistors operating at high voltage and for second transistors operating at the lower voltage, and formation of a second layer of gate oxide (5) with a second thickness on third portions for cells of the memory; deposition of a first polysilicon layer to define gate electrodes (8,9) for first transistors and floating gate electrodes (7) for the memory cells; deposition of an interpolysilicon dielectric layer (18) so as to leave the interpolysilicon dielectric layer on the gate electrodes (8,9) of first transistors and on the floating gate electrodes (7); formation, on the second portions (1), of a third gate oxide layer (24) with a third thickness less than the first thickness of the first gate oxide layer (3); deposition of a second polysilicon layer (25) to define gate structures (29) of the memory cells, and gate electrodes (26,27) of second transistors and polysilicon covers (80,90) for the gate electrodes (8,9) of first transistors.

Abstract translation: 一种制造集成电路的方法，该集成电路包括在高电压下工作的存储器和在比该存储器低的电压下操作的逻辑电路：在半导体衬底的第一和第二部分上形成具有第一厚度的栅极氧化物（3）的第一层 1），其分别用于在高电压下操作的第一晶体管和用于在较低电压下操作的第二晶体管，以及在存储器的单元的第三部分上形成具有第二厚度的栅极氧化物（5）的第二层; 沉积第一多晶硅层以限定用于第一晶体管的栅电极（8,9）和用于存储器单元的浮栅电极（7）; 沉积多晶硅介电层（18），以便在第一晶体管的栅电极（8,9）和浮栅电极（7）上留下多晶硅介电层; 在第二部分（1）上形成具有小于第一栅极氧化物层（3）的第一厚度的第三厚度的第三栅极氧化物层（24）; 沉积第二多晶硅层（25）以限定存储器单元的栅极结构（29），以及第二晶体管的栅电极（26,27）和用于栅电极（8,9）的多晶硅覆盖物（80,90） 第一晶体管。