Digital-to-analog conversion circuit
    1.
    发明公开
    Digital-to-analog conversion circuit 有权
    数字 - 模拟wandlerschaltung

    公开(公告)号:EP1179889A1

    公开(公告)日:2002-02-13

    申请号:EP00830573.2

    申请日:2000-08-10

    Inventor: Pinna, Carlo

    CPC classification number: H03M1/0665 H03M1/747 H03M3/502

    Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal. In an embodiment the digital to analog conversion circuit able to transform a digital input signal (5) having n bit in an output analog signal (6) comprise: a thermometric decoder (60) having said digital input signal (5) in input and able to produce said signal (SW1-SW7) having a thermometric code with 2 n -1 bit in output; a digital to analog converter (21, 31) with modular elements (C1-C7, R1-R7) including 2 n -1 controlled switches (I1-I7); a shift register (61) able to receive said digital signal (T1-T7) having 2 n -1 bit in an data input and able to produce 2 n -1 control signals (SW1-SW7) of said controlled switches (I1-I7) in output; a delay circuit (62) of said of digital input signal (5) having the output connected to a shift input (64) of said shift register (61) and able to produce a delayed digital signal in output as to make said digital signal (T1-T7) having 2 n -1 bit shift by a number of bit equal to the value of said delayed digital signal; characterised by further comprising a generator (91) of a digital random number selected in a range of prefixed values and having a prefixed probability of occurrence; an adder node (90) able to receive said random digital number and said delayed digital signal in input whose output is connected to said shift input (64) of said shift register (61).

    Abstract translation: 本发明涉及一种数模转换电路,能够对具有测温码的信号中具有n位的输入数字信号进行变换,并将其转换为模拟输出信号。 在一个实施例中,能够转换在输出模拟信号(6)中具有n位的数字输入信号(5)的数模转换电路包括:具有所述数字输入信号(5)的输入和能力的测温解码器(60) 以产生具有输出中具有2 -1位的温度代码的所述信号(SW1-SW7) 具有包括2 n -1个受控开关(I1-I7)的模块化元件(C1-C7,R1-R7)的数模转换器(21,31); 能够在数据输入端接收具有2 n比特的数字信号(T1-T7)的移位寄存器(61),能够产生所述受控开关的2 n -1个控制信号(SW1-SW7) (I1-I7)输出; 所述数字输入信号(5)的延迟电路(62)具有连接到所述移位寄存器(61)的移位输入端(64)的输出,并且能够在输出中产生延迟的数字信号,以使所述数字信号( T1-T7),其具有等于所述延迟数字信号的值的位数; 其特征在于还包括在预定值的范围内选择并具有预先出现概率的数字随机数的发生器(91) 能够接收所述随机数字数字的加法器节点(90)和输出端的所述延迟的数字信号,其输出端连接到所述移位寄存器(61)的所述移位输入端(64)。

    Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter
    2.
    发明公开
    Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter 有权
    一种用于在最后Integrateurs的输出的Σ-Δ转换器和相关联的换能器增加的抖动信号的方法

    公开(公告)号:EP1727287A1

    公开(公告)日:2006-11-29

    申请号:EP05425374.5

    申请日:2005-05-27

    CPC classification number: H03M3/332 H03M3/424 H03M3/454

    Abstract: A single-ended or differential single-stage or multi-stage sigma-delta analog-to-digital converter comprises at least a switched-capacitor integrator having a switched-capacitor structure, to an input of which a signal to be sampled is applied, and an amplifier in cascade thereto, and has circuit means coupled to the amplifier for feeding an analog dither signal to a virtual ground node of the amplifier.

    Abstract translation: 单端或差分单级或多级Σ-Δ模拟到数字转换器包括具有至少一个开关电容器积分器的开关电容器结构,在其中的输入信号被采样被施加 并在级联放大器于此,并且电路装置,耦合到所述放大器用于馈送到模拟抖动信号到所述放大器的虚拟接地节点。

    Boosted sampling circuit and relative method of driving
    3.
    发明公开
    Boosted sampling circuit and relative method of driving 有权
    供电电压增加采样和相关的驱动

    公开(公告)号:EP1494357A1

    公开(公告)日:2005-01-05

    申请号:EP03425439.1

    申请日:2003-07-03

    CPC classification number: G11C27/024 H03M1/1245

    Abstract: A boosted sampling circuit easy to realize, the input voltage of which may be greater than the maximum voltage level allowed by prior art circuits or even equal to the supply voltage, is disclosed.
    This result is attained by connecting the control nodes of the switches M2, M3 and M4 to the input node while the first control phase F1D is active, and by connecting a current terminal of the transistor M2 to a certain voltage for protecting it from breakdowns.
    A relative method of driving a boosted sampling circuit is also disclosed.

    Boosted switch device for a sampler of an analogue/digital converter, and operating method thereof
    6.
    发明公开
    Boosted switch device for a sampler of an analogue/digital converter, and operating method thereof 审中-公开
    与模拟/数字转换器的拾取控制增加,和它的操作方法切换装置

    公开(公告)号:EP1168619A1

    公开(公告)日:2002-01-02

    申请号:EP00830430.5

    申请日:2000-06-19

    CPC classification number: H03K17/165 G11C27/02 H03K17/063

    Abstract: The boosted switch device (12") comprises an input terminal (2) and an output terminal (8); a supply line (60) set to a supply potential (V cc ) ; a ground line (60) set to a ground potential (V GND ); a transistor (64) connected between the input and output terminals (2, 8); a capacitor (68); and a switch device (74, 76, 78, 80, 82) connecting the capacitor (68) between the supply line (60) and the ground line (60), when the transistor is off, and between the input terminal (2) and the control terminal (66) of the transistor (64), when the transistor (64) is on.

    Abstract translation: (A接地线60)设置(到接地电位;所述升压开关设备(12“)输入端的方法包括:(2),并在输出端子(8);一电源线(60)设置为供给电压(VCC) VGND);一个晶体管(64),连接在所述输入和输出端子(2之间,8),电容器(68);以及连接之间的电容器(68)的开关装置(74,76,78,80,82) 供应管线(60)与接地线(60)当晶体管关断时,与输入端子(2)和所述晶体管(64)当晶体管(64)是上的控制端子(66)之间。

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