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    Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more different sectors
    3.
    发明公开
    Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more different sectors 有权
    架构是闪速EEPROM，而擦除或一个或多个其它扇区的编程，读取同一时间。

    公开(公告)号：EP1327992A1

    公开(公告)日：2003-07-16

    申请号：EP02425009.4

    申请日：2002-01-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Silvagni, Andrea ,  Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C16/08 ,  G11C8/16

    CPC classification number: G11C16/08 ,  G11C2216/22

    Abstract: A non volatile memory device based on the realization of two distinct orders of main wordlines and bitlines, distinguishing a first order as main read wordlines (MWLR) and main read bitlines (MBLR) and a second order as main program wordlines (MWLP) and main program bitlines (MBLP), to each pair of main lines of which are associated a certain number of local lines, for example four lines, in each sector of subdivision of the array of memory cells, according to the criteria that are normally used in the so called hierarchical decoding structures of a memory whose array of elementary memory cells is subdivided in banks and/or sectors.
    Distinct decoders are associated to the two distinct orders of main wordlines and of main bitlines, the relative inputs of which are two address buses for reading and programming/erasing operations, respectively. A first address bus (RADD) coming from the address input pads of the device, through commonly used circuits, realizes a path for the read addresses to be input to main read wordlines decoders and to main read bitlines decoders. The input of the decoders of the main program wordlines and of the main program bitlines is, on the contrary, provided by an internal bus (PADD), generated by controllers of program and erase operations that control all the verification and load operations of data to be programmed.

    Abstract translation: 基础上，实现主字线和位线的两个不同的订单的非易失性存储器装置中，区分第一顺序作为主要的读字线（MWLR）和主读出的位线（MBLR）和第二顺序主程序字线（MWLP）和主 其中的程序位线（MBLP）到每对的主线相关联的本地线路一定数量，例如四个行存储器单元的阵列的细分的每个扇区，雅鼎的准则并通常在所使用的 所谓的初级的存储器数组，其存储单元是细分在银行和/或扇区的层次解码处理的结构。 不同的解码器关联到主字线和主位线的两个不同的订单，其中的相对输入是两个地址总线用于读取和编程/擦除分别操作，。 第一地址总线（RADD）从装置的地址输入焊盘来，通过通常使用的电路中，实现了路径的读出地址将被输入到主读出字线和解码器到主读位线解码器。 节目字的主线和主程序位线的解码器的输入是，与此相反，通过内部总线上提供（PADD），通过程序的控制器产生和擦除操作做了控制的所有数据的验证和装载操作，以 进行编程。

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