公开(公告)号：EP1587066A3

公开(公告)日：2005-11-02

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

Abstract: A write driver (510;1210) driving a write current (IL) through a head connected to the write head (570;1270) by an interconnect (560;1260). The write driver (510;1210) includes a circuit (514.556;1214,1256;1340) matching output resistance to the odd characteristic impedance of the interconnect (560;1260) and a voltage boosting circuit (512;1212). The voltage boosting circuit (512;1212) is connected between a supply voltage (VCC) and a voltage reference (VEE), and includes at least a current generator (440,1140), such as a MOS transistor, connected to the input node (422;1122) of a single capacitor (420;1120).

Abstract translation: 写入驱动器（510; 1210）通过互连（560; 1260）通过连接到写入头（570; 1270）的头来驱动写入电流（IL）。 写入驱动器（510; 1210）包括匹配互连（560; 1260）和升压电路（512; 1212）的奇特征阻抗的输出电阻的电路（514.556; 1214,1256; 1340）。 升压电路（512; 1212）连接在电源电压（VCC）和电压基准（VEE）之间，并且包括至少一个电流发生器（440,1140），例如MOS晶体管，连接到输入节点 （420; 1120）的电容器（422; 1122）。

公开(公告)号：EP1587066A2

公开(公告)日：2005-10-19

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

Abstract: A write driver (510;1210) driving a write current (IL) through a head connected to the write head (570;1270) by an interconnect (560;1260). The write driver (510;1210) includes a circuit (514.556;1214,1256;1340) matching output resistance to the odd characteristic impedance of the interconnect (560;1260) and a voltage boosting circuit (512;1212). The voltage boosting circuit (512;1212) is connected between a supply voltage (VCC) and a voltage reference (VEE), and includes at least a current generator (440,1140), such as a MOS transistor, connected to the input node (422;1122) of a single capacitor (420;1120).

Abstract translation: 通过驱动连接到写头的头的写入电流（IL）（570; 1270）; A写入驱动器（1210 510）通过向间连接（560; 1260）。 写入驱动器（510; 1210）包括电路（514556; 1214.1256; 1340）输出电阻匹配到互连的奇数特性阻抗（560; 1260）和一个升压电路（512; 1212）。 升压电路（512; 1212）被连接在电源电压（VCC）和参考电压（VEE）之间，并且至少包括一个电流发生器（440.1140）：如一个MOS晶体管，连接到所述输入节点 （422; 1122）的单个电容器的（420; 1120）。

公开(公告)号：EP1587066B1

公开(公告)日：2009-04-08

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

公开(公告)号：EP1130768A3

公开(公告)日：2003-09-17

申请号：EP01100815.8

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Cazzaniga, Marco ,  Venca, Alessandro

IPC: H03D7/14 ,  H03F3/45

CPC classification number: G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

公开(公告)号：EP1130768A2

公开(公告)日：2001-09-05

申请号：EP01100815.8

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Cazzaniga, Marco ,  Venca, Alessandro

IPC: H03D7/14

CPC classification number: G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair.
This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

Abstract translation: 本发明涉及一种低电源模拟乘法器，其包括一对差分单元（10,11），每个单元包括具有耦合发射器的一对双极晶体管（2,3; 6,7）。 每个单元（10,11）的第一晶体管（2,6）在其基极上接收输入信号（Vin +，Vin-），并且其集电极通过偏置构件（4）耦合到第一参考电压（Vcc） ，8）。 有利地，每个单元的第二晶体管（3,7）是二极管配置，并且单元在对应于每对中的第二晶体管（3,7）的基极端子的公共节点（A）处互连。 这种乘法器可以提供非常低的电压，并且仍然表现出高的运行速率以及输出信号的减少的谐波失真，即使高峰值幅度高于600 mV的输入信号也是如此。