公开(公告)号：EP1130773B1

公开(公告)日：2007-01-03

申请号：EP00830154.1

申请日：2000-02-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Rossi, Augusto ,  Betti, Giorgio ,  Cazzaniga, Marco

IPC: H03H17/02 ,  G11B20/10

CPC classification number: H03H17/0211 ,  G11B20/10009

公开(公告)号：EP0847137B9

公开(公告)日：2004-10-27

申请号：EP96830603.5

申请日：1996-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： Rezzi, Francesco ,  Castello, Rinaldo ,  Cazzaniga, Marco ,  Bietti,Ivan

IPC: H03H11/04

CPC classification number: H03H11/0433

公开(公告)号：EP1130773A1

公开(公告)日：2001-09-05

申请号：EP00830154.1

申请日：2000-02-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Rossi, Augusto ,  Betti, Giorgio ,  Cazzaniga, Marco

IPC: H03H17/02 ,  G11B20/10

CPC classification number: H03H17/0211 ,  G11B20/10009

Abstract: The invention relates to a time-continous FIR (Finite Impulse Response) filter whereby a Hilbert transform can be implemented. The filter comprises a cascade of delay cells connected between an input terminal of the filter and an output terminal; constant filter coefficients (cO,...,cn) and a programmable time delay (Td) of the programmable filter cells are provided.
The invention also relates to a filtering method effective to enable use of this Hilbert FIR filter structure for processing signals originated by the reading of data from magnetic storage media which employ perpendicular recording.

Abstract translation: 本发明涉及一种可实现希尔伯特变换的时间连续的FIR（有限脉冲响应）滤波器。 滤波器包括连接在滤波器的输入端和输出端之间的级联延迟单元; 提供了可编程滤波器单元的恒定滤波器系数（c0，...，cn）和可编程时间延迟（Td）。 本发明还涉及一种有效使得能够使用这种希尔伯特FIR滤波器结构来处理由采用垂直记录的磁存储介质读取数据所产生的信号的滤波方法。

公开(公告)号：EP1146639A3

公开(公告)日：2003-04-16

申请号：EP01100814.1

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Portaluri, Salvatore ,  Cazzaniga, Marco ,  Castello, Rinaldo

IPC: H03H11/04

CPC classification number: H03H11/0422

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

公开(公告)号：EP0847137B1

公开(公告)日：2004-03-03

申请号：EP96830603.5

申请日：1996-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： Rezzi, Francesco ,  Castello, Rinaldo ,  Cazzaniga, Marco ,  Bietti,Ivan

IPC: H03H11/04

CPC classification number: H03H11/0433

公开(公告)号：EP1146639B1

公开(公告)日：2004-06-09

申请号：EP01100814.1

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Portaluri, Salvatore ,  Cazzaniga, Marco ,  Castello, Rinaldo

IPC: H03H11/04

CPC classification number: H03H11/0422

公开(公告)号：EP1130768A3

公开(公告)日：2003-09-17

申请号：EP01100815.8

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Cazzaniga, Marco ,  Venca, Alessandro

IPC: H03D7/14 ,  H03F3/45

CPC classification number: G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

公开(公告)号：EP1146639A2

公开(公告)日：2001-10-17

申请号：EP01100814.1

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Portaluri, Salvatore ,  Cazzaniga, Marco ,  Castello, Rinaldo

IPC: H03H11/04

CPC classification number: H03H11/0422

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters.
This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc).
Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

Abstract translation: 本发明涉及前馈型具有可编程零，特别是对于合成时间连续滤波器的电路结构。 这个结构包括至少一个互连节点（A）相互连接，并且连接的第一信号（Vin）输入第一小区的（IN）（14）之间和输出端子的一对扩增的细胞（14,15）（U） 所述第二小区（15，每个单元（14,15）包括一对晶体管（10.2，6.7），其具有共同的导通端子，并具有分别耦合到第一电压基准的其他导通端子（VCC ）通过respectivement偏置构件（3.4; 9.11）所述结构还包括一个电路腿（13）连接所述第一单元（14）到输出端（U）的一个节点（X）并包括一个晶体管（。 8），其具有连接到所述第一单元（14），连接到所述输出端（U）的第一导通端子，以及耦合到第二电压基准（GND）通过第二传导端的节点（X）的控制端子 电容器（CC），因此，释放“零”可以在零极点复杂的计划，以改善的右半平面上引入 组增益平坦化。

公开(公告)号：EP1130768A2

公开(公告)日：2001-09-05

申请号：EP01100815.8

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Cazzaniga, Marco ,  Venca, Alessandro

IPC: H03D7/14

CPC classification number: G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair.
This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

Abstract translation: 本发明涉及一种低电源模拟乘法器，其包括一对差分单元（10,11），每个单元包括具有耦合发射器的一对双极晶体管（2,3; 6,7）。 每个单元（10,11）的第一晶体管（2,6）在其基极上接收输入信号（Vin +，Vin-），并且其集电极通过偏置构件（4）耦合到第一参考电压（Vcc） ，8）。 有利地，每个单元的第二晶体管（3,7）是二极管配置，并且单元在对应于每对中的第二晶体管（3,7）的基极端子的公共节点（A）处互连。 这种乘法器可以提供非常低的电压，并且仍然表现出高的运行速率以及输出信号的减少的谐波失真，即使高峰值幅度高于600 mV的输入信号也是如此。