公开(公告)号：EP1217656A1

公开(公告)日：2002-06-26

申请号：EP00830835.5

申请日：2000-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Mottura, Marta ,  Fischetti, Alessandra ,  Ferrera, Marco ,  Zerbini, Bernardino ,  Bombonati, Mauro

IPC: H01L21/762 ,  H01L21/20

CPC classification number: H01L21/2007 ,  H01L21/76256

Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer (8) comprising a first semiconductor material layer (9), a second semiconductor material layer (21), and a dielectric material layer (10) arranged between the first and the second semiconductor material layer (8, 9); and removing the first semiconductor material layer (9) initially by mechanically thinning the first semiconductor material layer (9), so as to form a residual conductive layer (9'), and subsequently by chemically removing the residual conductive layer (9'). In one application, the multi-layer wafer (8) is bonded to a first wafer (1) of semiconductor material, with the second semiconductor material layer (21) facing the first wafer (1), after micro-electromechanical structures (37) have been formed in the second semiconductor material layer (21) of the multi-layer wafer.

Abstract translation: 提供（8）包括一个第一半导体材料层（9），第二半导体材料层（21），和一个电介质材料层的多层晶片：一种用于在多层晶片的制造部件，包括下列步骤 （10）在第一和第二半导体材料层之间布置（8,9）; 以及去除所述第一半导体材料层（9）最初由机械减薄所述第一半导体材料层（9），以便形成一个残余导电层（9“），并且随后通过化学方法除去残留的导电层（9”）。 在一个应用中，该多层晶片（8）结合到半导体材料的第一晶片（1），具有面向所述第一晶片的第二半导体材料层（21）（1），后微机电结构（37） havebeen形成在多层晶片的所述第二半导体材料层（21）。