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    Structure for electrically connecting a first body of semiconductor material overlaid by a second body of semiconductor material, composite structure using the electric connection structure, and manufacturing process thereof
    1.
    发明公开
    Structure for electrically connecting a first body of semiconductor material overlaid by a second body of semiconductor material, composite structure using the electric connection structure, and manufacturing process thereof 有权
    一种用于电连接第一，具有覆盖的第二半导体材料，该电连接用复合材料和它们的制备结构

    公开(公告)号：EP1151962A1

    公开(公告)日：2001-11-07

    申请号：EP00830314.1

    申请日：2000-04-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mastromatteo, Ubaldo ,  Ghironi, Fabrizio ,  Aina, Roberto ,  Bombonati, Mauro

    IPC: B81C3/00 ,  H01L25/065 ,  H01L23/48 ,  G11B19/20

    CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01322

    Abstract: The electric connection structure connects a first silicon body (10) to conductive regions (29, 30) provided on the surface of a second silicon body (1) arranged on the first body (10). The electric connection structure comprises at least one plug region (3) of silicon, which extends through the second body (1); at least one insulation region (2a, 6) laterally surrounding the plug region (3); and at least one conductive electromechanical connection region (23) arranged between the first body (10) and the second body (1), and in electrical contact with the plug region (3) and with conductive regions (15-19; 40) of the first body (10). To form the plug region (3), trenches (2a) are dug in a first wafer (1) and are filled, at least partially, with insulating material (6). Next, the plug region (3) is fixed to a metal region (23) provided on a second wafer (10), by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. Subsequently, the first wafer (1) is thinned until the trenches (2a) and electrical connections (29, 30) are formed on the free face of the first wafer.

    Abstract translation: 的电连接结构连接的第一硅体（10），以提供布置在第一主体（10）的第二硅本体（1）的表面上的导电区域（29，30）。 的电连接结构包括硅中的至少一个插塞区域（3），它通过所述第二主体延伸（1）; 至少一个绝缘区域（2A，6）横向围绕所述插头区域（3）; 和至少一个导电机电连接区域（23）与第一主体（10）和第二本体（1）之间以及在与所述插塞区域（3）的电接触，并与导电区域布置（15-19; 40）的 第一主体（10）。 为了形成插头区域（3），沟槽（2a）的挖在第一晶片（1）和被填充时，至少部分地与绝缘材料（6）。 接着，将插塞区域（3）被固定到设置在第二晶片（10）通过进行低温热处理这导致金属与硅之间的化学反应的金属区（23）。 随后，第一晶片（1）被减薄，直至沟槽（2a）和电连接（29，30）在所述第一晶片的自由面上形成。

    Process for manufacturing components in a semiconductor material with reduction in the starting wafer thickness
    2.
    发明公开
    Process for manufacturing components in a semiconductor material with reduction in the starting wafer thickness 审中-公开
    制造组件的过程中的半导体晶片与减少盘的初始厚度的

    公开(公告)号：EP1217656A1

    公开(公告)日：2002-06-26

    申请号：EP00830835.5

    申请日：2000-12-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mottura, Marta ,  Fischetti, Alessandra ,  Ferrera, Marco ,  Zerbini, Bernardino ,  Bombonati, Mauro

    IPC: H01L21/762 ,  H01L21/20

    CPC classification number: H01L21/2007 ,  H01L21/76256

    Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer (8) comprising a first semiconductor material layer (9), a second semiconductor material layer (21), and a dielectric material layer (10) arranged between the first and the second semiconductor material layer (8, 9); and removing the first semiconductor material layer (9) initially by mechanically thinning the first semiconductor material layer (9), so as to form a residual conductive layer (9'), and subsequently by chemically removing the residual conductive layer (9'). In one application, the multi-layer wafer (8) is bonded to a first wafer (1) of semiconductor material, with the second semiconductor material layer (21) facing the first wafer (1), after micro-electromechanical structures (37) have been formed in the second semiconductor material layer (21) of the multi-layer wafer.

    Abstract translation: 提供（8）包括一个第一半导体材料层（9），第二半导体材料层（21），和一个电介质材料层的多层晶片：一种用于在多层晶片的制造部件，包括下列步骤 （10）在第一和第二半导体材料层之间布置（8,9）; 以及去除所述第一半导体材料层（9）最初由机械减薄所述第一半导体材料层（9），以便形成一个残余导电层（9“），并且随后通过化学方法除去残留的导电层（9”）。 在一个应用中，该多层晶片（8）结合到半导体材料的第一晶片（1），具有面向所述第一晶片的第二半导体材料层（21）（1），后微机电结构（37） havebeen形成在多层晶片的所述第二半导体材料层（21）。

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