公开(公告)号：EP2264753A2

公开(公告)日：2010-12-22

申请号：EP10183038.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/74 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (500). The method includes the steps of providing an SOI substrate (505) including a semiconductor substrate (510), an insulating layer (515) on the semiconductor substrate, and a semiconductor starting layer (512) on the insulating layer, the substrate and the starting layer being of a first type of conductivity, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (542) of the first type of conductivity embedding the starting layer on the insulating layer, forming at least one insulating trench (558) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (560) and at least one further insulated region (561), and integrating components (580) of the device in the insulated regions, the components being insulated from the substrate by the insulating layer; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (520) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, each contact trench clearing a corresponding portion (530b,530s) of the starting layer, of the insulating layer and of the substrate, implanting dopants of a second type of conductivity different from the first type into at least part of the cleared portions, wherein the epitaxial growing is further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material, the dopants diffusing during the epitaxial growing to form an insulating region (545) of the second type of conductivity enclosing the at least one contact trench of each further insulated region, and integrating further components (580) of the device in each further insulated region, the further components being insulated from the substrate by a junction formed by the corresponding insulating region with the active layer and/or the substrate when reverse-biased.

Abstract translation: 提出了一种用于制造集成电子设备（500）的方法。 该方法包括以下步骤：提供包括半导体衬底（510），在半导体衬底上的绝缘层（515）以及在绝缘层上的半导体起始层（512）的SOI衬底（505），衬底和起始 所述外延生长工艺被施加到所述起始层以获得在所述绝缘层上嵌入所述起始层的第一类型的导电性的更厚的半导体活性层（542） 形成从有源层的暴露表面延伸到绝缘层的至少一个绝缘沟槽（558），所述至少一个绝缘沟槽将有源层分隔成绝缘区域（560）和至少一个另外的绝缘区域（561）， 以及将所述器件的部件（580）集成在所述绝缘区域中，所述部件通过所述绝缘层与所述衬底绝缘; 在根据本发明实施例的解决方案中，所述方法还包括：在执行外延生长工艺的步骤之前，形成至少一个接触沟槽（520），所述接触沟槽从起始层的暴露表面延伸到衬底， 每个另外的绝缘区域，每个接触沟槽清除起始层，绝缘层和衬底的对应部分（530b，530s）;将不同于第一类型的第二类型导电性的掺杂物注入至少部分 其中外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充每个接触沟槽，掺杂剂在外延生长期间扩散以形成第二类型导电性的绝缘区域（545） 每个另外的绝缘区域的至少一个接触沟槽，并且还将每个进一步的器件的组件（580）集成在一起 所述另外的部件在反向偏置时通过由所述对应的绝缘区域与所述有源层和/或所述衬底形成的结与所述衬底绝缘。

公开(公告)号：EP1435533A1

公开(公告)日：2004-07-07

申请号：EP02425811.3

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Di Turi, Luigi ,  Favretto, Ivana ,  Mottura, Marta

IPC: G02B6/12

CPC classification number: G02B6/136 ,  G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  G02B2006/12173

Abstract: A method of producing a waveguide (20) with a rounded core integrated in a substrate (1), including phases of:

forming a lower cladding (3) of the guide supported by the substrate;
etching said lower cladding to define a concave region delimited by a curved surface (11) and extending along the axis of propagation;
providing on a free surface (12) of said lower cladding a layer (13) of doped material filling the concave region (4) to form a first portion (17) of the core in contact with the curved surface;
etching the layer of doped material so that only sufficient volume of doped material for the waveguide core remains;
heating the doped material so that it forms a rounded core due to surface tension and the concave region of the cladding.

Abstract translation: 一种制造具有集成在衬底（1）中的圆形芯的波导（20）的方法，包括：形成由衬底支撑的引导件的下包层（3）; 蚀刻所述下部包层以限定由弯曲表面（11）限定并沿着传播轴线延伸的凹形区域; 在所述下包层的自由表面（12）上提供填充所述凹区（4）的掺杂材料层（13），以形成与所述弯曲表面接触的所述芯的第一部分（17）; 蚀刻掺杂材料层，使得仅剩余足够体积的用于波导芯的掺杂材料; 加热掺杂的材料，使得它由于表面张力和包层的凹形区域而形成圆形芯。

公开(公告)号：EP2264752A2

公开(公告)日：2010-12-22

申请号：EP10182985.1

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/74 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (400) of the SOI type. The method includes the steps of providing an SOI substrate (105) including a semiconductor substrate (110), an insulating layer (115) on the semiconductor substrate, and a semiconductor starting layer (112) on the insulating layer, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (142) embedding the starting layer on the insulating layer, forming at least one insulating trench (405) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (415) and at least one further insulated region (425), and integrating components (420) of the device in the insulated regions; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (120) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, wherein each contact trench clears a corresponding portion (130b,130s) of the starting layer, of the insulating layer and of the substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material gettering impurities of the active layer, the gettered impurities in the at least one further insulated region being segregated from the insulated regions.

Abstract translation: 提出了一种制造SOI型集成电子器件（400）的方法。 该方法包括以下步骤：提供包括半导体衬底（110），半导体衬底上的绝缘层（115）和绝缘层上的半导体起始层（112）的SOI衬底（105），执行外延生长工艺 ，外延生长工艺被施加到起始层，以获得将起始层嵌入绝缘层上的更厚的半导体有源层（142），形成从活性层的暴露表面延伸到至少一个绝缘沟槽（405） 绝缘层，所述至少一个绝缘沟槽将所述有源层分隔成绝缘区域（415）和至少一个另外的绝缘区域（425），以及将所述器件的部件（420）集成在所述绝缘区域中; 在根据本发明的实施例的解决方案中，该方法还包括在进行外延生长工艺的步骤之前，形成从起始层的暴露表面延伸到衬底的至少一个接触沟槽（120），对应于 每个另外的绝缘区域，其中每个接触沟槽清除起始层，绝缘层和衬底的对应部分（130b，130s），外延生长被进一步施加到清除部分，从而至少部分地填充每个接触沟槽 利用吸收有源层的杂质的半导体材料，至少一个另外的绝缘区域中的杂质杂质与绝缘区域分离。

公开(公告)号：EP1296374A1

公开(公告)日：2003-03-26

申请号：EP01830590.4

申请日：2001-09-14

Applicant: STMicroelectronics S.r.l. ,  Hewlett Packard Company, a Delaware Corporation

Inventor： Mastromatteo, Ubaldo ,  Bombonati, Mauro ,  Morin, Daniela ,  Mottura, Marta ,  Marchi, Mauro

IPC: H01L23/48 ,  B81B7/00 ,  H01L21/18

CPC classification number: B81C1/00269 ,  H01L21/185 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13164 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/013

Abstract: A process for bonding two distinct substrates that integrate microsystems, comprising the steps of: making micro-integrated devices in at least one of the two substrates using microelectronic processing techniques; and bonding said substrates. The bonding is performed by making on a first substrate (33) bonding regions (32) of deformable material and by pressing said substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate (34). The bonding regions are preferably formed by a thick layer (30) made of a material chosen from among aluminium, copper and nickel, covered by a thin layer (31) made of a material chosen from between palladium and platinum. Spacing regions (25') guarantee exact spacing between the two wafers.

Abstract translation: 一种用于接合两个不同的基板的制造方法做了集成微，包括以下步骤：制作集成在使用微电子加工技术在两个基底中的至少一个微器件; 和键合所述基底上。 接合被执行，通过使可变形材料制成的第一衬底（33）键合区域（32），并通过按压所述基板中的一个对另一个以变形的接合区域和以使它们与所述第二基片起化学反应（34） ， 接合区域优选通过由选自铝，铜和镍中选择的材料的一厚层（30），通过由从钯和铂之间选择的材料的薄层（31）覆盖而形成。 间隔区（25“），保证了两个晶片之间的精确间距。

公开(公告)号：EP2264753A3

公开(公告)日：2011-04-20

申请号：EP10183038.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/76 ,  H01L21/84 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (500). The method includes the steps of providing an SOI substrate (505) including a semiconductor substrate (510), an insulating layer (515) on the semiconductor substrate, and a semiconductor starting layer (512) on the insulating layer, the substrate and the starting layer being of a first type of conductivity, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (542) of the first type of conductivity embedding the starting layer on the insulating layer, forming at least one insulating trench (558) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (560) and at least one further insulated region (561), and integrating components (580) of the device in the insulated regions, the components being insulated from the substrate by the insulating layer; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (520) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, each contact trench clearing a corresponding portion (530b,530s) of the starting layer, of the insulating layer and of the substrate, implanting dopants of a second type of conductivity different from the first type into at least part of the cleared portions, wherein the epitaxial growing is further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material, the dopants diffusing during the epitaxial growing to form an insulating region (545) of the second type of conductivity enclosing the at least one contact trench of each further insulated region, and integrating further components (580) of the device in each further insulated region, the further components being insulated from the substrate by a junction formed by the corresponding insulating region with the active layer and/or the substrate when reverse-biased.

公开(公告)号：EP1659640A1

公开(公告)日：2006-05-24

申请号：EP04425867.1

申请日：2004-11-19

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Riboli, Paolo ,  Zanotti, Luca ,  Palmieri, Michele ,  Mottura, Marta

IPC: H01L31/18 ,  H01L31/068 ,  H01L21/762

CPC classification number: H01L31/1804 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of fabricating a wafer-size photovoltaic cell module capable of drastically reducing the overall costs of photovoltaic cells of enhanced efficiency realized on a monocrystalline silicon substrate comprises the steps of:

defining an integrated cellular structure, of a light converting monolateral or bilateral junction diode in the epitaxially grown detachable layer, including a first deposited metal current collecting terminal of the diode;
laminating onto the surface the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions;
immersing the wafer in a hydrofluoric acid solution causing detachment of the processed epitaxially grown silicon layer laminated with the film of optical grade plastic material;
polishing the surface of separation of the detached processed epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a relatively low temperature tolerable by the film of optical grade plastic material.

Abstract translation: 制造能够大幅度地减少的实现上的单晶硅衬底增强效率的光伏电池的总成本的晶片尺寸太阳能电池组件的方法，包括以下步骤：光的集成蜂窝结构的 - 定义，转换单边或双边结二极管 在外延生长层可拆卸的，包括第一熔敷金属集流二极管的端子; 到表面上的处理外延生长可分离层层压的光学级塑料材料，以氢氟酸溶液腐蚀的膜; 浸渍在曹景伟层叠有光学级塑料材料制成的膜经处理的外延生长的硅层的剥离氢氟酸溶液的晶片; 抛光处理分离外延生长层的分离表面以及形成第二金属电流在相对低的温度下的光学级塑料材料制成的膜可容忍收集二极管通过金属的掩蔽沉积的终端。

公开(公告)号：EP1217656A1

公开(公告)日：2002-06-26

申请号：EP00830835.5

申请日：2000-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Mottura, Marta ,  Fischetti, Alessandra ,  Ferrera, Marco ,  Zerbini, Bernardino ,  Bombonati, Mauro

IPC: H01L21/762 ,  H01L21/20

CPC classification number: H01L21/2007 ,  H01L21/76256

Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer (8) comprising a first semiconductor material layer (9), a second semiconductor material layer (21), and a dielectric material layer (10) arranged between the first and the second semiconductor material layer (8, 9); and removing the first semiconductor material layer (9) initially by mechanically thinning the first semiconductor material layer (9), so as to form a residual conductive layer (9'), and subsequently by chemically removing the residual conductive layer (9'). In one application, the multi-layer wafer (8) is bonded to a first wafer (1) of semiconductor material, with the second semiconductor material layer (21) facing the first wafer (1), after micro-electromechanical structures (37) have been formed in the second semiconductor material layer (21) of the multi-layer wafer.

Abstract translation: 提供（8）包括一个第一半导体材料层（9），第二半导体材料层（21），和一个电介质材料层的多层晶片：一种用于在多层晶片的制造部件，包括下列步骤 （10）在第一和第二半导体材料层之间布置（8,9）; 以及去除所述第一半导体材料层（9）最初由机械减薄所述第一半导体材料层（9），以便形成一个残余导电层（9“），并且随后通过化学方法除去残留的导电层（9”）。 在一个应用中，该多层晶片（8）结合到半导体材料的第一晶片（1），具有面向所述第一晶片的第二半导体材料层（21）（1），后微机电结构（37） havebeen形成在多层晶片的所述第二半导体材料层（21）。

公开(公告)号：EP2264752A3

公开(公告)日：2011-04-20

申请号：EP10182985.1

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/322 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (400) of the SOI type. The method includes the steps of providing an SOI substrate (105) including a semiconductor substrate (110), an insulating layer (115) on the semiconductor substrate, and a semiconductor starting layer (112) on the insulating layer, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (142) embedding the starting layer on the insulating layer, forming at least one insulating trench (405) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (415) and at least one further insulated region (425), and integrating components (420) of the device in the insulated regions; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (120) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, wherein each contact trench clears a corresponding portion (130b,130s) of the starting layer, of the insulating layer and of the substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material gettering impurities of the active layer, the gettered impurities in the at least one further insulated region being segregated from the insulated regions.

公开(公告)号：EP1873822A1

公开(公告)日：2008-01-02

申请号：EP06116133.7

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Toia, Fabrizio Fausto Renzo ,  Mottura, Marta

IPC: H01L21/762

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76898 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device (100, 100', 760) is proposed. The device is integrated in a chip (705) including at least one stacked layer having a front surface (140, 708) and a rear surface (743) opposite the front surface, the device including: an insulating trench (120,120', 718) insulating an active region (125, 747) of the chip, the insulating trench having a section across each plane parallel to the front surface extending along a longitudinal line (207, 207'), and a front-rear contact (430,436, 440) electrically contacting the front surface to the rear surface in the active region, wherein the section of the insulating trench has a non-uniform width along the longitudinal line, and/or the device further includes at least one further insulating trench (170) within the active region.

Abstract translation: 一种电子装置（100，100”，760）的提议。 该装置被集成在一个芯片（705）包括具有前表面（140，708）的至少一个堆叠层和后表面（743）与前表面相对，该装置包括：一个绝缘槽（120,120”，718） 绝缘的芯片，具有横跨每一个部分中的绝缘沟槽，并平行于前表面沿纵向线（207“207）（430.436，440）延伸的前，后接触面的有源区（125，747） 电接触的前表面到后表面在有源区，worin绝缘沟槽的部分具有沿着所述纵向线的非均匀的宽度，和/或该设备进一步包括至少一个另外的内绝缘沟槽（170） 有源区。

公开(公告)号：EP1873821A1

公开(公告)日：2008-01-02

申请号：EP06116123.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/74

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method for manufacturing an integrated electronic device (100;400;500) is proposed. The method comprises the steps of: providing an SOI substrate (105;505) comprising a semiconductor substrate (110;510), an insulating layer (115;515) on the semiconductor substrate, and a semiconductor starting layer (112;512) on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer (142;542) on the insulating layer for integrating components of the device, and forming at least one contact trench (120;520) extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion (130b,130s;530b,530s) of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract translation: 提出了一种用于制造集成电子装置（100; 400; 500）的方法。 该方法包括以下步骤：提供包括半导体衬底（110; 510），半导体衬底上的绝缘层（115; 515）和半导体起始层（112; 512）上的SOI衬底（105; 505） 绝缘层; 外延生长所述起始层以在所述绝缘层上获得半导体有源层（142; 542），用于对所述器件的部件进行积分，以及形成从所述起始层的暴露表面延伸到所述至少一个接触沟槽（120; 520） 在外延生长起始层的步骤之前的半导体衬底，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的对应部分（130b，130s; 530b，530s），外延生长被进一步应用 到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。