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    Integrated device for use in a monostable circuit
    7.
    发明公开
    Integrated device for use in a monostable circuit 失效
    在einer monostabilen Schaltung verwendbare integrierte Vorrichtung

    公开(公告)号：EP0909030A1

    公开(公告)日：1999-04-14

    申请号：EP97830506.8

    申请日：1997-10-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Genova, Angelo ,  Gariboldi, Roberto ,  Cantone, Giuseppe

    IPC: H03K3/0232 ,  H03K3/355

    CPC classification number: H03K3/011 ,  H03K3/0232 ,  H03K3/355

    Abstract: Integrated device (202) for use in a monostable circuit (200), the integrated device (202) having a programming terminal (103) able to be linked to external resistive means (Rext) so as to programme the duration of a non-stable state of the circuit (200) and comprising a comparator (120) having a first (+) and a second (-) input terminal and an output terminal for generating an output signal (Vout) of the circuit (200), capacitive means (C) linked to the first input terminal (+) of the comparator (120) so as to apply thereto a voltage (Vc) correlated with the voltage on the capacitive means (C), control means (SW,115) linked to the first input terminal (+) of the comparator (120) so as to switch the circuit (200) to the non-stable state, and means (M1, M2) for sending a current (Iref1) which passes through the resistive means (Rext) to the capacitive means (C), in which the programming terminal (103) is linked to the second input terminal (-) of the comparator (120) so as to apply thereto a voltage (Vref1) correlated with the voltage on the resistive means (Rext).

    Abstract translation: 用于单稳态电路（200）的集成器件（202），该集成器件（202）具有能够连接到外部电阻器件（Rext）的编程端子（103），以便编程不稳定的持续时间 电路（200）的状态，并且包括具有第一（+）和第二（ - ）输入端子的比较器（120）和用于产生电路（200）的输出信号（Vout）的输出端子，电容装置 C）连接到比较器（120）的第一输入端（+），以便向其施加与电容装置（C）上的电压相关的电压（Vc）;与第一输入端连接的控制装置（SW，115） （120）的输入端（+），将电路（200）切换到非稳定状态;以及用于发送通过电阻装置（Rext）的电流（Iref1）的装置（M1，M2） 到电容装置（C），其中编程端子（103）连接到比较器（120）的第二输入端子（ - ），以便施加 到与电阻装置（Rext）上的电压相关的电压（Vref1）。

    Protection circuit for controlling the gate voltage of a high voltage LDMOS transistor
    8.
    发明公开
    Protection circuit for controlling the gate voltage of a high voltage LDMOS transistor 失效
    Schutzschaltung zur Steuerung der Gatterspannung eines Hochspannungs-LDMOS晶体管

    公开(公告)号：EP0887931A1

    公开(公告)日：1998-12-30

    申请号：EP97830296.6

    申请日：1997-06-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tarantola, Mario ,  Cantone, Giuseppe ,  Genova, Angelo ,  Gariboldi, Roberto

    IPC: H03K17/06

    CPC classification number: H03K17/08122 ,  H03K17/063

    Abstract: A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap (Cp) capacitor charged by a diode (D1) connected to the supply node (Vs) of the circuit, by an (IO1) inverter driven by a logic control circuit in function of a first Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase where the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, comprises further a second inverter (M1, M2), functionally referred to the charging node of said bootstrap (Cp) capacitor and to the voltage of the output node (A) of said inverter (IO1) and having an input coupled to said second logic signal (UVLOb) and an output coupled to the gate node of said LDMOS transistor (LD), for preventing accidental undue switch-on of the LDMOS transistor.

    Abstract translation: 一种用于通过用作源极跟随器级的LDMOS集成晶体管（LD）对电容（C）进行充电的电路，以通过经由自举（Cp）电容器充电的自举（Cp）电容器模拟电容的高电压充电二极管的方式被控制 和由第一低栅极驱动信号的逻辑控制电路驱动的（IO1）反相器和第二逻辑信号（UVLOb）连接的电路的供电节点（Vs）的二极管（D1） 在电源电压（Vs）低于集成电路的最小接通电压的阶段中，还包括在功能上称为所述自举（Cp）电容器的充电节点的第二反相器（M1，M2），并且 所述反相器（IO1）的输出节点（A）的电压和耦合到所述第二逻辑信号（UVLOb）的输入端和耦合到所述LDMOS晶体管（LD）的栅极节点的输出端，用于防止意外不适当的开关 - 在LDMOS晶体管上。

    Circuit for generating a reference voltage and detecting an undervoltage of a supply voltage and corresponding method
    9.
    发明公开
    Circuit for generating a reference voltage and detecting an undervoltage of a supply voltage and corresponding method 失效
    用于产生参考电压，并检测电源电压的下降和相关联的方法的电路装置

    公开(公告)号：EP0733959A1

    公开(公告)日：1996-09-25

    申请号：EP95830111.1

    申请日：1995-03-24

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Gariboldi, Roberto ,  Pulvirenti, Francesco

    IPC: G05F3/26 ,  G05F3/28

    CPC classification number: G11C5/147 ,  G05F1/465 ,  G05F3/267

    Abstract: A circuit for generating a reference voltage and detecting a drop in a supply voltage, comprising at least one threshold comparator (12) having an input terminal (IN) and an output terminal, and a voltage divider (14) connected between a first supply voltage reference (Vs) and a second voltage reference (GND) and connected to the input terminal (IN) of the comparator (12), further provides for the output terminal (OUT) of said comparator (12) to be connected to the input terminal (IN) through at least one feedback network comprising at least one current generator (CG1).
    The feedback network further comprises a buffer block (13) having an input terminal connected to said comparator (12) and a first output terminal (DO) connected to a switch (SW) which is connected between a circuit node (X2) of said voltage divider (14) and the second voltage reference (GND).

    Abstract translation: 连接在第一电源电压之间，用于产生参考电压，并检测在供电电压下降的电路，包括：具有输入端（IN）上，并输出终端的至少一个阈值比较器（12），和一个电压分压器（14） 参考（VS）和一个第二电压基准（GND）和连接到所述比较器（12）的输入端（IN），还提供了用于所述比较器（12）的输出端（OUT）被连接到输入端 （IN）通过至少一个反馈网络，其包括至少一个电流发生器（CG1）。 反馈网络还包括具有连接到连接到被连接在所述电压的电路节点（X2）之间的开关（SW）所有的所述比较器（12）和第一输出端（DO）输入端一个缓冲器块（13） 除法器（14）和所述第二电压基准（GND）。

    Driving circuit for a field effect transistor in final semibridge stage
    10.
    发明公开
    Driving circuit for a field effect transistor in final semibridge stage 失效
    Treiberschaltungfüreinen Feldeffekttistoristor在einerHalbbrückenausgangsstufe。

    公开(公告)号：EP0608667A1

    公开(公告)日：1994-08-03

    申请号：EP93830034.0

    申请日：1993-01-29

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

    IPC: H03K17/687

    CPC classification number: H03K17/0414 ,  H03K17/04123 ,  H03K17/687

    Abstract: A drive circuit for a field-effect transistor (MFET1) which has a drain terminal connected to the positive pole (+Vcc) of the power supply and a source terminal connected to a load (OUT).
    The circuit has circuit means for turning off the field-effect transistor (MFET1) which comprises a first transistor (M1) connected between the gate terminal of the field-effect transistor (MFET1) and the negative pole (GND) of the power supply.
    Said first transistor (MFET1) is driven by an operational amplifier (M3,M4,MR1,MR2,MR3) which has inverting and non-inverting terminals connected to the gate and source terminals of the field-effect transistor (MFET1) respectively.

    Abstract translation: 用于场效应晶体管（MFET1）的驱动电路，其具有连接到电源的正极（+ Vcc）的漏极端子和连接到负载（OUT）的源极端子。 电路具有用于截止场效应晶体管（MFET1）的电路装置，该场效应晶体管包括连接在场效应晶体管（MFET1）的栅极端子和电源的负极（GND）之间的第一晶体管（M1）。 所述第一晶体管（MFET1）由运算放大器（M3，M4，MR1，MR2，MR3）驱动，其运算放大器分别具有连接到场效应晶体管（MFET1）的栅极和源极端子的反相和非反相端子。

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