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    A non-volatile memory device supporting high-parallelism test at wafer level
    1.
    发明公开
    A non-volatile memory device supporting high-parallelism test at wafer level 有权
    EinnichtflüchtigerSpeicher mitUnterstützungvon hochparallelem Test auf Waferebene

    公开(公告)号：EP1672647A1

    公开(公告)日：2006-06-21

    申请号：EP04106609.3

    申请日：2004-12-15

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Lomazzi, Guido ,  Renna, Ilaria ,  Maccarrone, Marco

    IPC: G11C29/00

    CPC classification number: G11C29/1201 ,  G11C16/04 ,  G11C29/006 ,  G11C29/16 ,  G11C29/46 ,  G11C2029/2602

    Abstract: A non-volatile memory device (100) is proposed. The non-volatile memory device includes a chip (105) of semiconductor material. The chip includes a memory (202) and control means (204,210,214) for performing a programming operation (314), an erasing operation (312) and a reading operation (316) on the memory in response to corresponding external commands. The chip further includes testing means (118, 120, 220, 225, 230) for performing at least one test process including the repetition of at least one of said operations by the control means, and a single access element (118) for enabling the testing means.

    Abstract translation: 提出了一种非易失性存储器件（100）。 非易失性存储器件包括半导体材料的芯片（105）。 芯片包括用于响应于相应的外部命令在存储器上执行编程操作（314），擦除操作（312）和读取操作（316）的存储器（202）和控制装置（204,210,214）。 所述芯片还包括用于执行至少一个测试过程的测试装置（118,120,220,225,230），所述测试装置包括由所述控制装置重复所述操作中的至少一个操作;以及单个访问元件（118） 测试手段。

    Fast programming method for nonvolatile memories, in particular flash memories, and related memory architecture
    3.
    发明公开
    Fast programming method for nonvolatile memories, in particular flash memories, and related memory architecture 有权
    为非易失性存储器，尤其是闪速存储器，以及类似的存储器架构快速编程方法

    公开(公告)号：EP1308964A1

    公开(公告)日：2003-05-07

    申请号：EP01830671.2

    申请日：2001-10-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Lomazzi, Guido ,  Mulatti, Jacopo ,  Surico, Stefano

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C2216/14 ,  G11C2216/16

    Abstract: The programming method includes the following steps: sequentially receiving (23, 27) a plurality of data words; temporarily storing (24, 29) each data word after its reception; and simultaneously writing (31, 35) in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments (25) an address counter and sends a "ready" signal (26). Upon reception of each new data word (27), the memory verifies whether the address associated thereto is in the same sector as the initial data word (28) and whether n data words have already been stored (30). If the sector is different, blind-programming step is terminated (35, 36) and the verifying is carried out (37); if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array (31), updates the address counter (25), and then sends the "ready" signal (26).

    Abstract translation: 该编程方法包括以下步骤：顺序地接收（23，27）的数据字的多个; 暂时存储（24，29）其接收之后每个数据字; 同时，并与存储数据字的在存储器阵列中的多个书写（31，35）并联连接。 接收和每个数据字的临时存储之后，存储器增量（25），以解决计数器并发送一个“就绪”信号（26）。 在每个新的数据字（27）的接收，所述存储器确认是否在其上的地址相关联是在相同的扇区，不论数据字已经被存储的所述初始数据字（28）和n（30）。 如果该扇区是不同的，盲的编程步骤被终止（35，36）和所述验证被执行（37）; 如果该扇区是相同的，但n个数据字已经被暂时存储，存储器写入所述存储器阵列中的暂时存储字（31）更新地址计数器（25），然后发送“准备”信号（26） ，

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