中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

40 records (took 0.052 seconds)

    PACKAGE FOR SEMICONDUCTOR DEVICES SENSITIVE TO MECHANICAL AND THERMO-MECHANICAL STRESSES, SUCH AS MEMS PRESSURE SENSORS
    2.
    发明申请
    PACKAGE FOR SEMICONDUCTOR DEVICES SENSITIVE TO MECHANICAL AND THERMO-MECHANICAL STRESSES, SUCH AS MEMS PRESSURE SENSORS 有权
    用于机械和机械应力敏感的半导体器件的封装，如MEMS压力传感器

    公开(公告)号：US20160146692A1

    公开(公告)日：2016-05-26

    申请号：US14861648

    申请日：2015-09-22

    Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS, INC.

    Inventor： Fulvio Vittorio Fontana ,  Jefferson Talledo

    IPC: G01L19/14

    CPC classification number: G01L19/148 ,  B81B7/0045 ,  B81C1/00325 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49575 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014

    Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.

    Abstract translation: 表面安装装置具有一个诸如ASIC的半导体材料，以及围绕该主体的封装。 该包装具有承载本体的基部区域，盖子和接触端子。 基部区域的杨氏模量低于5MPa。 为了形成装置，主体附接到支撑框架，该支撑框架包括由空腔分开的接触端子和模片垫; 接合线焊接到主体和接触端子; 将弹性材料模制成至少围绕主体的侧面，填充支撑框架的空腔并覆盖接触端子上的接合线的端部; 并且帽固定到基部区域。 然后蚀刻掉芯片焊盘。

    Semiconductor device and corresponding method
    5.
    发明授权
    Semiconductor device and corresponding method 有权

    公开(公告)号：US11152289B2

    公开(公告)日：2021-10-19

    申请号：US16406911

    申请日：2019-05-08

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Michele Derai

    IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

    Method of integrating capacitors on lead frame in semiconductor devices
    6.
    发明授权
    Method of integrating capacitors on lead frame in semiconductor devices 有权

    公开(公告)号：US10283441B2

    公开(公告)日：2019-05-07

    申请号：US15282619

    申请日：2016-09-30

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L49/02

    Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.

    SHIELDED ENCAPSULATING STRUCTURE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    SHIELDED ENCAPSULATING STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    其屏蔽结构及其制造方法

    公开(公告)号：US20150217993A1

    公开(公告)日：2015-08-06

    申请号：US14686540

    申请日：2015-04-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Alex Gritti

    IPC: B81B7/00 ,  H05K9/00

    CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L2224/48091 ,  H01L2224/48137 ,  H04R1/021 ,  H04R1/04 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/029 ,  H05K9/0009 ,  H01L2924/00014

    Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.

    Abstract translation: 一个或多个实施例涉及封装结构，包括：具有第一表面并且容纳至少一个导电焊盘的衬底，所述至少一个导电焊盘面向第一表面延伸并且被配置为在参考电压下电耦合到导通端子; 盖构件，其设置在离基板的第一表面一定距离处; 以及在基板和盖构件之间延伸的壳体壁。 衬底，盖构件和壳体壁限定空腔，其在封装结构内部并容纳导电垫。 此外，在腔内部还存在至少一个导电结构，其在盖构件和导电垫之间延伸并与之电接触，用于将盖构件电连接到导电端子。

Patent Agency Ranking