公开(公告)号：EP1742257B1

公开(公告)日：2012-09-05

申请号：EP05425483.4

申请日：2005-07-08

Applicant: STMicroelectronics Srl

Inventor： Arena, Giuseppe ,  Donato, Caterina ,  Camalleri, Cateno Marco ,  Magri', Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

公开(公告)号：EP2309545A3

公开(公告)日：2011-10-12

申请号：EP10015764.3

申请日：2004-09-30

Applicant: STMicroelectronics Srl

Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/732 ,  H01L29/861 ,  H01L29/417 ,  H01L29/06 ,  H01L21/336 ,  H01L21/331 ,  H01L21/329 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

Abstract: A vertical power semiconductor device and corresponding realisation method, the device being integrated on a semiconductor substrate (10) and comprising respective gate (20), source (25) and drain (30) areas, realised in an epitaxial layer (40) arranged on said semiconductor substrate (10) and comprising respective gate (21), source (26) and drain (31) metallisations realised by means of a first metallisation level as well as gate (60), source (65) and drain (70) terminals or pads realised by means of a second metallisation level. The device is configured as a set of modular areas (100) extending parallel to each other, each having a rectangular elongate source area (25) perimetrically surrounded by a narrow gate area (20), and separated from each other by regions (30a) with drain area (30) extending parallel and connected at the opposite ends thereof to a second closed region (30b) with drain area (30) forming a device outer peripheral edge; as well as a sinker structure (45) extending perpendicularly to the substrate and formed by a grid of sinker (S) located below both the first parallel regions (30a) and the second closed region (30b) with drain area (30) in order to favour a conductive channel for a current coming from the source area (25) and directed towards the drain area (30) across the substrate (10).

公开(公告)号：EP2309545A2

公开(公告)日：2011-04-13

申请号：EP10015764.3

申请日：2004-09-30

Applicant: STMicroelectronics Srl

Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

Abstract: A vertical power semiconductor device and corresponding realisation method, the device being integrated on a semiconductor substrate (10) and comprising respective gate (20), source (25) and drain (30) areas, realised in an epitaxial layer (40) arranged on said semiconductor substrate (10) and comprising respective gate (21), source (26) and drain (31) metallisations realised by means of a first metallisation level as well as gate (60), source (65) and drain (70) terminals or pads realised by means of a second metallisation level. The device is configured as a set of modular areas (100) extending parallel to each other, each having a rectangular elongate source area (25) perimetrically surrounded by a narrow gate area (20), and separated from each other by regions (30a) with drain area (30) extending parallel and connected at the opposite ends thereof to a second closed region (30b) with drain area (30) forming a device outer peripheral edge; as well as a sinker structure (45) extending perpendicularly to the substrate and formed by a grid of sinker (S) located below both the first parallel regions (30a) and the second closed region (30b) with drain area (30) in order to favour a conductive channel for a current coming from the source area (25) and directed towards the drain area (30) across the substrate (10).

Abstract translation: 一种垂直功率半导体器件及其相应的实现方法，所述器件集成在半导体衬底（10）上并且包括在外延层（40）中实现的相应的栅极（20），源极（25）和漏极（30）区域， 所述半导体衬底（10）包括相应的栅极（21），通过第一金属化层以及栅极（60），源极（65）和漏极（70）端子实现的源极（26）和漏极（31） 或通过第二金属化层实现的焊盘。 该装置被配置为一组彼此平行延伸的模块化区域（100），每个模块化区域具有由窄的栅极区域（20）沿周向环绕的矩形细长源区域（25），并且通过区域（30a）彼此分开， 其中漏极区域（30）平行地延伸并且在其相对端处连接到第二封闭区域（30b），其中漏极区域（30）形成装置外周边缘; 以及垂直于衬底延伸并且由位于第一平行区域（30a）下方的沉降片（S）网格和具有排出区域（30）的第二封闭区域（30b）依次形成的沉降片结构（45） 以支持用于来自源极区域（25）的电流的导电沟道，并跨过衬底（10）指向漏极区域（30）。

公开(公告)号：EP1659638B1

公开(公告)日：2011-01-12

申请号：EP05025288.1

申请日：2005-11-18

Applicant: STMicroelectronics Srl

Inventor： Magri', Angelo ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712

Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors (2) having respective gate structures (12) and comprising a gate oxide (7) with double thickness having a thick central part (8) and lateral portions (9) of reduced thickness. Such device exhibiting gate structures (12) comprising first gate conductive portions (13) overlapped onto said lateral portions (9) of reduced thickness to define, for the elementary Mos transistors (2), the gate electrodes, as well as a conductive structure or mesh (14). Such conductive structure (14) comprising a plurality of second conductive portions (15) overlapped onto the thick central part (8) of gate oxide (7) and interconnected to each other and to the first gate conductive portions (13) by means of a plurality of conducive bridges (16). The present invention further relates to a method for realising the power MOS device.