公开(公告)号：US20230207467A1

公开(公告)日：2023-06-29

申请号：US18145490

申请日：2022-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngseok PARK ,  Eunji Yang ,  Junyoung Kwon

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L23/53252 ,  H01L23/5226 ,  H01L21/311 ,  H01L21/321

Abstract: Provided are an interconnector and an electronic apparatus including the interconnector. The interconnector includes: a metal layer; a dielectric layer surrounding at least a portion of the metal layer; and an interlayer disposed between the metal layer and the dielectric layer and including a ternary metal oxide.

公开(公告)号：US11961898B2

公开(公告)日：2024-04-16

申请号：US17546303

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan Nguyen ,  Minsu Seol ,  Junyoung Kwon ,  Hyeonjin Shin ,  Minseok Yoo ,  Yeonchoo Cho

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/463

CPC classification number: H01L29/66045 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/304 ,  H01L21/463 ,  H01L29/66969

Abstract: A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.

公开(公告)号：US12191392B2

公开(公告)日：2025-01-07

申请号：US17505955

申请日：2021-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan Nguyen ,  Minsu Seol ,  Eunkyu Lee ,  Junyoung Kwon ,  Hyeonjin Shin ,  Minseok Yoo

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/24

Abstract: A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.

公开(公告)号：US20240047528A1

公开(公告)日：2024-02-08

申请号：US18156049

申请日：2023-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Keunwook Shin ,  Alum Jung ,  Junyoung Kwon ,  Kyung-Eun Byun ,  Minseok Yoo

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66969

Abstract: A semiconductor device may include a two-dimensional (2D) material layer, a source electrode and a drain electrode spaced apart from each other on the 2D material layer, a gate insulating layer and a gate electrode on the 2D material layer between the source electrode and the drain electrode, and graphene layers on both sides of the gate insulating layer. The 2D material layer may include a 2D semiconductor material having a polycrystalline structure. The 2D material layer may include a sheet member and a protrusion. The sheet member may extend along one plane. The protrusion may extend in one direction perpendicular to the one plane. The graphene layer may cover a part of the sheet member and the protrusion.

公开(公告)号：US11935790B2

公开(公告)日：2024-03-19

申请号：US17370480

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Seol ,  Minhyun Lee ,  Junyoung Kwon ,  Hyeonjin Shin ,  Minseok Yoo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0259 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/78696

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

公开(公告)号：US20240021683A1

公开(公告)日：2024-01-18

申请号：US18152976

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Duseop YOON ,  Junyoung Kwon ,  Minsu Seol ,  Minseok Yoo ,  Kyung-Eun Byun

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/41733 ,  H01L29/401 ,  H01L29/45 ,  H01L29/24

Abstract: A semiconductor device may include a two-dimensional material layer, one or more metal islands on the two-dimensional material layer, and a metal layer covering the metal islands on the two-dimensional material layer. The semiconductor device may be manufactured by a method including forming metal islands on a two-dimensional material layer using a redox method and forming a metal layer covering the metal islands on the two-dimensional material layer.