公开(公告)号：EP3772103A1

公开(公告)日：2021-02-03

申请号：EP20188770.0

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHOI, Yoonyoung ,  LEE, Byunghyun ,  KU, Byeongjoo ,  KIM, Seungjin ,  PARK, Sangjae ,  BAE, Jinwoo ,  LEE, Hangeol ,  CHOI, Bowo ,  HONG, Hyunsil

IPC: H01L27/108 ,  H01L49/02

Abstract: The present disclosure provides capacitor forming methods which may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

公开(公告)号：EP4274400A1

公开(公告)日：2023-11-08

申请号：EP23156274.5

申请日：2023-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KU, Byeongjoo ,  KIM, Keunnam ,  LEE, Wonsok ,  JEONG, Moonyoung ,  CHO, Min Hee

IPC: H10B12/00 ,  H01L29/786

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, first and second word lines adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the first and second vertical portions is located at a height that is lower than or equal to the uppermost surface of the bit line.

公开(公告)号：EP4283681A1

公开(公告)日：2023-11-29

申请号：EP23159022.5

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KIM, Keunnam ,  LEE, Kiseok ,  KU, Byeongjoo

IPC: H01L29/10 ,  H01L29/786 ,  H10B12/00 ,  H01L27/12

Abstract: A semiconductor memory device includes: a substrate and an insulating layer on the substrate, first and second peripheral active regions on the insulating layer, each having a first surface and an opposing second surface, a device isolation layer between the first and second peripheral active regions to isolate the first and second peripheral active regions, a bit line connected to at least one of the first surface of the first peripheral active region and the first surface of the second peripheral active region, a first gate insulating layer provided on the second surfaces of the first and second peripheral active regions, a first peripheral gate electrode disposed on the first gate insulating layer and a second peripheral gate electrode disposed on the second gate insulating layer, and a contact pattern connected to the bit line, wherein each of the first peripheral active region and the second peripheral active region is floated in relation to the substrate by the insulating layer.