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公开(公告)号：US10177781B2
公开(公告)日：2019-01-08
申请号：US13925781
申请日：2013-06-24
Applicant: Silicon Laboratories Inc.
Inventor： Louis Nervegna , Bruce Del Signore
Abstract: A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.
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Patent Agency Ranking
2.发明申请CAPACITANCE-TO-DIGITAL CONVERTER UTILIZING DIGITAL FEEDBACK AND AUXILIARY DAC 有权使用数字反馈和辅助DAC的电容数字转换器公开(公告)号：US20160182081A1
公开(公告)日：2016-06-23
申请号：US14575167
申请日：2014-12-18
Applicant: Silicon Laboratories Inc.
Inventor： Michael H. Perrott , Louis Nervegna
IPC: H03M3/00
CPC classification number: H03M3/362 , G01D5/24 , G01N27/26 , G01R17/105 , G01R27/2605 , H03M3/464 , H03M3/476 , H03M3/496 , Y10T307/729
Abstract: A capacitance-to-digital converter circuit s a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in the bridge circuit. The sense capacitors vary according to a sensed parameter. Auxiliary capacitor digital to analog converters (DACs) are coupled to the capacitor bridge circuit to cancel the sensed difference. An analog to digital converter (ADC) receives a signal generated by the capacitor bridge circuit and the auxiliary capacitor DACs and converts the received signal to a digital signal. A digital accumulator accumulates the ADC output, whose output represents the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output is used to control the auxiliary capacitor DACs to offset the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output also provides the basis for the capacitance-to-digital circuit output.
Abstract translation: 电容 - 数字转换器电路是用于感测桥式电路中的感测电容器和固定电容器之间的电容差的电容器桥接电路。 感测电容器根据感测参数而变化。 辅助电容器数模转换器（DAC）耦合到电容器桥接电路以消除感测到的差异。 模数转换器（ADC）接收由电容器桥电路和辅助电容DAC产生的信号，并将接收的信号转换为数字信号。 数字累加器累加ADC输出，其输出表示感测电容器和固定电容器之间的电容差。 累加器输出用于控制辅助电容DAC以抵消感测电容器和固定电容器之间的电容差。 累加器输出也为电容 - 数字电路输出提供了基础。
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3.发明授权Capacitance-to-digital converter utilizing digital feedback and auxiliary DAC 有权采用数字反馈和辅助DAC的电容数字转换器公开(公告)号：US09385747B1
公开(公告)日：2016-07-05
申请号：US14575167
申请日：2014-12-18
Applicant: Silicon Laboratories Inc.
Inventor： Michael H. Perrott , Louis Nervegna
IPC: H03M3/00
CPC classification number: H03M3/362 , G01D5/24 , G01N27/26 , G01R17/105 , G01R27/2605 , H03M3/464 , H03M3/476 , H03M3/496 , Y10T307/729
Abstract: A capacitance-to-digital converter circuit utilizes a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in the bridge circuit. The sense capacitors vary according to a sensed parameter. Auxiliary capacitor digital to analog converters (DACs) are coupled to the capacitor bridge circuit to cancel the sensed difference. An analog to digital converter (ADC) receives a signal generated by the capacitor bridge circuit and the auxiliary capacitor DACs and converts the received signal to a digital signal. A digital accumulator accumulates the ADC output, whose output represents the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output is used to control the auxiliary capacitor DACs to offset the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output also provides the basis for the capacitance-to-digital circuit output.
Abstract translation: 电容数字转换器电路利用电容器桥电路来感测桥式电路中感测电容器和固定电容器之间的电容差。 感测电容器根据感测参数而变化。 辅助电容器数模转换器（DAC）耦合到电容器桥接电路以消除感测到的差异。 模数转换器（ADC）接收由电容器桥电路和辅助电容DAC产生的信号，并将接收的信号转换为数字信号。 数字累加器累加ADC输出，其输出表示感测电容器和固定电容器之间的电容差。 累加器输出用于控制辅助电容DAC以抵消感测电容器和固定电容器之间的电容差。 累加器输出也为电容 - 数字电路输出提供了基础。
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公开(公告)号：US20140375374A1
公开(公告)日：2014-12-25
申请号：US13954955
申请日：2013-07-30
Applicant: Silicon Laboratories Inc.
Inventor： Louis Nervegna , Bruce Del Signore
IPC: G01R27/26
CPC classification number: H03M3/362 , G01D5/24 , G01N27/26 , G01R17/105 , G01R27/2605 , H03M3/464 , H03M3/476 , H03M3/496 , Y10T307/729
Abstract: An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.
Abstract translation: 积分器电路包括包括第一和第二输入以及第一和第二输出的开关电容器桥。 开关电容器桥被配置为每单位时间间隔采样第一和第二参考电压两次。 积分器电路还包括积分器，其耦合到第一和第二输出，并且被配置为将每单位时间间隔中两次倾倒的第一和第二输出的电荷积分。
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5.发明申请公开(公告)号：US20160025664A1
公开(公告)日：2016-01-28
申请号：US14532723
申请日：2014-11-04
Applicant: Silicon Laboratories Inc.
Inventor： Emmanuel P. Quevy , Louis Nervegna , Jeremy R. Hui
CPC classification number: B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227
Abstract: Trapped sacrificial structures and thin-film encapsulation methods that may be implemented to manufacture trapped sacrificial structures such as relative humidity sensor structures, and spacer structures that protect adjacent semiconductor structures extending above a semiconductor die substrate from being contacted by a molding tool or other semiconductor processing tool in an area of a die substrate adjacent the spacer structures.
Abstract translation: 捕获的牺牲结构和薄膜封装方法可用于制造捕获的牺牲结构，例如相对湿度传感器结构，以及保护在半导体管芯基板之上延伸的相邻半导体结构不被模具或其它半导体加工件接触的间隔结构 工具在与衬垫结构相邻的管芯衬底的区域中。
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公开(公告)号：US09157937B2
公开(公告)日：2015-10-13
申请号：US13954955
申请日：2013-07-30
Applicant: Silicon Laboratories Inc.
Inventor： Louis Nervegna , Bruce Del Signore
CPC classification number: H03M3/362 , G01D5/24 , G01N27/26 , G01R17/105 , G01R27/2605 , H03M3/464 , H03M3/476 , H03M3/496 , Y10T307/729
Abstract: An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.
Abstract translation: 积分器电路包括包括第一和第二输入以及第一和第二输出的开关电容器桥。 开关电容器桥被配置为每单位时间间隔采样第一和第二参考电压两次。 积分器电路还包括积分器，其耦合到第一和第二输出，并且被配置为将每单位时间间隔中两次倾倒的第一和第二输出的电荷积分。
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