公开(公告)号：US09685473B2

公开(公告)日：2017-06-20

申请号：US15135219

申请日：2016-04-21

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Jae Young Park ,  Won Ho Lee

IPC: H04N9/64 ,  H04N9/083 ,  H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  H01L27/146 ,  H04N5/361 ,  H04N5/3745

CPC classification number: H01L27/14623 ,  H01L27/14607 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14649 ,  H04N5/361 ,  H04N5/3745 ,  H04N9/045

Abstract: A 4-color pixel image sensor having a visible color noise reduction function in a near infrared ray (NIR) pixel may include an active pixel region having a plurality of photodiodes, a plurality of first metal layers, a plurality of color filters, a first NIR pixel and a micro-lens, which are stacked, wherein the plurality of photodiodes are arranged in series and the plurality of color filters are formed to be adjacent to each other in series; an NIR optical black pixel region having a plurality of photodiodes and a second NIR pixel, which are stacked, wherein the plurality of photodiodes are arranged in series; and a visible optical black pixel region having a plurality of photodiodes, a second metal layer, a plurality of color filters and a micro-lens, which are stacked, wherein the plurality of photodiodes are arranged in series, and the plurality of color filters are formed to be adjacent to each other in series, wherein the active pixel region, the NIR optical black pixel region and the visible optical black pixel region are arranged on a same substrate in series.

公开(公告)号：US20150115330A1

公开(公告)日：2015-04-30

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。

公开(公告)号：US09553120B2

公开(公告)日：2017-01-24

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。