公开(公告)号：US20150115330A1

公开(公告)日：2015-04-30

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。

公开(公告)号：US09337228B2

公开(公告)日：2016-05-10

申请号：US14468843

申请日：2014-08-26

Applicant: SiliconFile Technologies Inc.

Inventor： Seung Hoon Sa ,  Young Ha Lee

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/1464

Abstract: An image sensor cell is divided into two chips, and a capacitor for noise reduction is formed in a bottom wafer in correspondence with a unit pixel of a top wafer in a stack chip package image sensor having a coupling structure of the two chips, so that noise characteristics of the image sensor are improved. A stack chip package image sensor includes: a first semiconductor chip that includes a photodiode, a transmission transistor, and a first conductive pad and outputs image charge, which is output from the photodiode, through the first conductive pad; and a second semiconductor chip that includes a drive transistor, a selection transistor, a reset transistor, and a second conductive pad and supplies a corresponding pixel with an output voltage corresponding to the image charge received from the first semiconductor chip through the second conductive pad. The second semiconductor chip includes a capacitor for noise reduction.

Abstract translation: 图像传感器单元被分成两个芯片，并且在具有两个芯片的耦合结构的堆叠芯片封装图像传感器中的顶部晶片的单位像素的底部晶片中形成用于降低噪声的电容器，使得 提高了图像传感器的噪声特性。 堆叠芯片封装图像传感器包括：第一半导体芯片，其包括光电二极管，透射晶体管和第一导电焊盘，并且通过第一导电焊盘输出从光电二极管输出的图像电荷; 以及包括驱动晶体管，选择晶体管，复位晶体管和第二导电焊盘的第二半导体芯片，并且通过第二导电焊盘向相应像素提供与从第一半导体芯片接收的图像电荷相对应的输出电压。 第二半导体芯片包括用于降噪的电容器。

公开(公告)号：US09553120B2

公开(公告)日：2017-01-24

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。